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OSCL-LXR

 
 

    


0001 Altera FPGA/HPS Bridge Driver
0002 
0003 Required properties:
0004 - regs          : base address and size for AXI bridge module
0005 - compatible    : Should contain one of:
0006                   "altr,socfpga-lwhps2fpga-bridge",
0007                   "altr,socfpga-hps2fpga-bridge", or
0008                   "altr,socfpga-fpga2hps-bridge"
0009 - resets        : Phandle and reset specifier for this bridge's reset
0010 - clocks        : Clocks used by this module.
0011 
0012 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
0013 
0014 Example:
0015         fpga_bridge0: fpga-bridge@ff400000 {
0016                 compatible = "altr,socfpga-lwhps2fpga-bridge";
0017                 reg = <0xff400000 0x100000>;
0018                 resets = <&rst LWHPS2FPGA_RESET>;
0019                 clocks = <&l4_main_clk>;
0020                 bridge-enable = <0>;
0021         };
0022 
0023         fpga_bridge1: fpga-bridge@ff500000 {
0024                 compatible = "altr,socfpga-hps2fpga-bridge";
0025                 reg = <0xff500000 0x10000>;
0026                 resets = <&rst HPS2FPGA_RESET>;
0027                 clocks = <&l4_main_clk>;
0028                 bridge-enable = <1>;
0029         };
0030 
0031         fpga_bridge2: fpga-bridge@ff600000 {
0032                 compatible = "altr,socfpga-fpga2hps-bridge";
0033                 reg = <0xff600000 0x100000>;
0034                 resets = <&rst FPGA2HPS_RESET>;
0035                 clocks = <&l4_main_clk>;
0036         };