0001 NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
0002
0003 The Boot and Power Management Processor (BPMP) is a co-processor found
0004 in Tegra210 SoC. It is designed to handle the early stages of the boot
0005 process as well as to assisting in entering deep low power state
0006 (suspend to ram), and also offloading DRAM memory clock scaling on
0007 some platforms. The binding document defines the resources that would
0008 be used by the BPMP T210 firmware driver, which can create the
0009 interprocessor communication (IPC) between the CPU and BPMP.
0010
0011 Required properties:
0012 - compatible
0013 Array of strings
0014 One of:
0015 - "nvidia,tegra210-bpmp"
0016 - reg: physical base address and length for HW synchornization primitives
0017 1) base address and length to Tegra 'atomics' hardware
0018 2) base address and length to Tegra 'semaphore' hardware
0019 - interrupts: specifies the interrupt number for receiving messages ("rx")
0020 and for triggering messages ("tx")
0021
0022 Optional properties:
0023 - #clock-cells : Should be 1 for platforms where DRAM clock control is
0024 offloaded to bpmp.
0025
0026 Example:
0027
0028 bpmp@70016000 {
0029 compatible = "nvidia,tegra210-bpmp";
0030 reg = <0x0 0x70016000 0x0 0x2000
0031 0x0 0x60001000 0x0 0x1000>;
0032 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
0033 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
0034 interrupt-names = "tx", "rx";
0035 };
