0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 The BPMP is a specific processor in Tegra chip, which is designed for
0015 booting process handling and offloading the power management, clock
0016 management, and reset control tasks from the CPU. The binding document
0017 defines the resources that would be used by the BPMP firmware driver,
0018 which can create the interprocessor communication (IPC) between the
0019 CPU and BPMP.
0020
0021 This node is a mailbox consumer. See the following files for details
0022 of the mailbox subsystem, and the specifiers implemented by the
0023 relevant provider(s):
0024
0025 - .../mailbox/mailbox.txt
0026 - .../mailbox/nvidia,tegra186-hsp.yaml
0027
0028 This node is a clock, power domain, and reset provider. See the
0029 following files for general documentation of those features, and the
0030 specifiers implemented by this node:
0031
0032 - .../clock/clock-bindings.txt
0033 - <dt-bindings/clock/tegra186-clock.h>
0034 - ../power/power-domain.yaml
0035 - <dt-bindings/power/tegra186-powergate.h>
0036 - .../reset/reset.txt
0037 - <dt-bindings/reset/tegra186-reset.h>
0038
0039 The BPMP implements some services which must be represented by
0040 separate nodes. For example, it can provide access to certain I2C
0041 controllers, and the I2C bindings represent each I2C controller as a
0042 device tree node. Such nodes should be nested directly inside the main
0043 BPMP node.
0044
0045 Software can determine whether a child node of the BPMP node
0046 represents a device by checking for a compatible property. Any node
0047 with a compatible property represents a device that can be
0048 instantiated. Nodes without a compatible property may be used to
0049 provide configuration information regarding the BPMP itself, although
0050 no such configuration nodes are currently defined by this binding.
0051
0052 The BPMP firmware defines no single global name-/numbering-space for
0053 such services. Put another way, the numbering scheme for I2C buses is
0054 distinct from the numbering scheme for any other service the BPMP may
0055 provide (e.g. a future hypothetical SPI bus service). As such, child
0056 device nodes will have no reg property, and the BPMP node will have no
0057 "#address-cells" or "#size-cells" property.
0058
0059 The shared memory area for the IPC TX and RX between CPU and BPMP are
0060 predefined and work on top of sysram, which is an SRAM inside the
0061 chip. See ".../sram/sram.yaml" for the bindings.
0062
0063 properties:
0064 compatible:
0065 oneOf:
0066 - items:
0067 - enum:
0068 - nvidia,tegra194-bpmp
0069 - nvidia,tegra234-bpmp
0070 - const: nvidia,tegra186-bpmp
0071 - const: nvidia,tegra186-bpmp
0072
0073 mboxes:
0074 description: A phandle and channel specifier for the mailbox used to
0075 communicate with the BPMP.
0076 maxItems: 1
0077
0078 shmem:
0079 description: List of the phandle to the TX and RX shared memory area
0080 that the IPC between CPU and BPMP is based on.
0081 minItems: 2
0082 maxItems: 2
0083
0084 "#clock-cells":
0085 const: 1
0086
0087 "#power-domain-cells":
0088 const: 1
0089
0090 "#reset-cells":
0091 const: 1
0092
0093 interconnects:
0094 items:
0095 - description: memory read client
0096 - description: memory write client
0097 - description: DMA read client
0098 - description: DMA write client
0099
0100 interconnect-names:
0101 items:
0102 - const: read
0103 - const: write
0104 - const: dma-mem # dma-read
0105 - const: dma-write
0106
0107 iommus:
0108 maxItems: 1
0109
0110 i2c:
0111 type: object
0112
0113 thermal:
0114 type: object
0115
0116 additionalProperties: false
0117
0118 required:
0119 - compatible
0120 - mboxes
0121 - shmem
0122 - "#clock-cells"
0123 - "#power-domain-cells"
0124 - "#reset-cells"
0125
0126 examples:
0127 - |
0128 #include <dt-bindings/interrupt-controller/arm-gic.h>
0129 #include <dt-bindings/mailbox/tegra186-hsp.h>
0130 #include <dt-bindings/memory/tegra186-mc.h>
0131
0132 hsp_top0: hsp@3c00000 {
0133 compatible = "nvidia,tegra186-hsp";
0134 reg = <0x03c00000 0xa0000>;
0135 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0136 interrupt-names = "doorbell";
0137 #mbox-cells = <2>;
0138 };
0139
0140 sram@30000000 {
0141 compatible = "nvidia,tegra186-sysram", "mmio-sram";
0142 reg = <0x30000000 0x50000>;
0143 #address-cells = <1>;
0144 #size-cells = <1>;
0145 ranges = <0x0 0x30000000 0x50000>;
0146
0147 cpu_bpmp_tx: sram@4e000 {
0148 reg = <0x4e000 0x1000>;
0149 label = "cpu-bpmp-tx";
0150 pool;
0151 };
0152
0153 cpu_bpmp_rx: sram@4f000 {
0154 reg = <0x4f000 0x1000>;
0155 label = "cpu-bpmp-rx";
0156 pool;
0157 };
0158 };
0159
0160 bpmp {
0161 compatible = "nvidia,tegra186-bpmp";
0162 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
0163 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
0164 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
0165 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
0166 interconnect-names = "read", "write", "dma-mem", "dma-write";
0167 iommus = <&smmu TEGRA186_SID_BPMP>;
0168 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
0169 TEGRA_HSP_DB_MASTER_BPMP>;
0170 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
0171 #clock-cells = <1>;
0172 #power-domain-cells = <1>;
0173 #reset-cells = <1>;
0174
0175 i2c {
0176 compatible = "nvidia,tegra186-bpmp-i2c";
0177 nvidia,bpmp-bus-id = <5>;
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180 };
0181
0182 thermal {
0183 compatible = "nvidia,tegra186-bpmp-thermal";
0184 #thermal-sensor-cells = <1>;
0185 };
0186 };
