0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX System Controller Firmware (SCFW)
0008
0009 maintainers:
0010 - Dong Aisheng <aisheng.dong@nxp.com>
0011
0012 description:
0013 The System Controller Firmware (SCFW) is a low-level system function
0014 which runs on a dedicated Cortex-M core to provide power, clock, and
0015 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
0016 (QM, QP), and i.MX8QX (QXP, DX).
0017 The AP communicates with the SC using a multi-ported MU module found
0018 in the LSIO subsystem. The current definition of this MU module provides
0019 5 remote AP connections to the SC to support up to 5 execution environments
0020 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
0021 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
0022 using the MSI bus.
0023
0024 properties:
0025 compatible:
0026 const: fsl,imx-scu
0027
0028 clock-controller:
0029 description:
0030 Clock controller node that provides the clocks controlled by the SCU
0031 $ref: /schemas/clock/fsl,scu-clk.yaml
0032
0033 ocotp:
0034 description:
0035 OCOTP controller node provided by the SCU
0036 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
0037
0038 keys:
0039 description:
0040 Keys provided by the SCU
0041 $ref: /schemas/input/fsl,scu-key.yaml
0042
0043 mboxes:
0044 description:
0045 A list of phandles of TX MU channels followed by a list of phandles of
0046 RX MU channels. The list may include at the end one more optional MU
0047 channel for general interrupt. The number of expected tx and rx
0048 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
0049 compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
0050 within the same MU instance. Cross instances are not allowed. The MU
0051 instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
0052 need to ensure that one is used that does not conflict with other
0053 execution environments such as ATF.
0054 oneOf:
0055 - items:
0056 - description: TX0 MU channel
0057 - description: RX0 MU channel
0058 - items:
0059 - description: TX0 MU channel
0060 - description: RX0 MU channel
0061 - description: optional MU channel for general interrupt
0062 - items:
0063 - description: TX0 MU channel
0064 - description: TX1 MU channel
0065 - description: TX2 MU channel
0066 - description: TX3 MU channel
0067 - description: RX0 MU channel
0068 - description: RX1 MU channel
0069 - description: RX2 MU channel
0070 - description: RX3 MU channel
0071 - items:
0072 - description: TX0 MU channel
0073 - description: TX1 MU channel
0074 - description: TX2 MU channel
0075 - description: TX3 MU channel
0076 - description: RX0 MU channel
0077 - description: RX1 MU channel
0078 - description: RX2 MU channel
0079 - description: RX3 MU channel
0080 - description: optional MU channel for general interrupt
0081
0082 mbox-names:
0083 oneOf:
0084 - items:
0085 - const: tx0
0086 - const: rx0
0087 - items:
0088 - const: tx0
0089 - const: rx0
0090 - const: gip3
0091 - items:
0092 - const: tx0
0093 - const: tx1
0094 - const: tx2
0095 - const: tx3
0096 - const: rx0
0097 - const: rx1
0098 - const: rx2
0099 - const: rx3
0100 - items:
0101 - const: tx0
0102 - const: tx1
0103 - const: tx2
0104 - const: tx3
0105 - const: rx0
0106 - const: rx1
0107 - const: rx2
0108 - const: rx3
0109 - const: gip3
0110
0111 pinctrl:
0112 description:
0113 Pin controller provided by the SCU
0114 $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
0115
0116 power-controller:
0117 description:
0118 Power domains controller node that provides the power domains
0119 controlled by the SCU
0120 $ref: /schemas/power/fsl,scu-pd.yaml
0121
0122 rtc:
0123 description:
0124 RTC controller provided by the SCU
0125 $ref: /schemas/rtc/fsl,scu-rtc.yaml
0126
0127 thermal-sensor:
0128 description:
0129 Thermal sensor provided by the SCU
0130 $ref: /schemas/thermal/fsl,scu-thermal.yaml
0131
0132 watchdog:
0133 description:
0134 Watchdog controller provided by the SCU
0135 $ref: /schemas/watchdog/fsl,scu-wdt.yaml
0136
0137 required:
0138 - compatible
0139 - mbox-names
0140 - mboxes
0141
0142 additionalProperties: false
0143
0144 examples:
0145 - |
0146 #include <dt-bindings/firmware/imx/rsrc.h>
0147 #include <dt-bindings/input/input.h>
0148 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
0149
0150 firmware {
0151 system-controller {
0152 compatible = "fsl,imx-scu";
0153 mbox-names = "tx0", "tx1", "tx2", "tx3",
0154 "rx0", "rx1", "rx2", "rx3",
0155 "gip3";
0156 mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
0157 &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
0158 &lsio_mu1 3 3>;
0159
0160 clock-controller {
0161 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
0162 #clock-cells = <2>;
0163 };
0164
0165 pinctrl {
0166 compatible = "fsl,imx8qxp-iomuxc";
0167
0168 pinctrl_lpuart0: lpuart0grp {
0169 fsl,pins = <
0170 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
0171 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
0172 >;
0173 };
0174 };
0175
0176 ocotp {
0177 compatible = "fsl,imx8qxp-scu-ocotp";
0178 #address-cells = <1>;
0179 #size-cells = <1>;
0180
0181 fec_mac0: mac@2c4 {
0182 reg = <0x2c4 6>;
0183 };
0184 };
0185
0186 power-controller {
0187 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
0188 #power-domain-cells = <1>;
0189 };
0190
0191 rtc {
0192 compatible = "fsl,imx8qxp-sc-rtc";
0193 };
0194
0195 keys {
0196 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
0197 linux,keycodes = <KEY_POWER>;
0198 };
0199
0200 watchdog {
0201 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
0202 timeout-sec = <60>;
0203 };
0204
0205 thermal-sensor {
0206 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
0207 #thermal-sensor-cells = <1>;
0208 };
0209 };
0210 };
