0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 # Copyright 2021 ARM Ltd.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: System Control and Management Interface (SCMI) Message Protocol bindings
0009
0010 maintainers:
0011 - Sudeep Holla <sudeep.holla@arm.com>
0012
0013 description: |
0014 The SCMI is intended to allow agents such as OSPM to manage various functions
0015 that are provided by the hardware platform it is running on, including power
0016 and performance functions.
0017
0018 This binding is intended to define the interface the firmware implementing
0019 the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
0020 and Management Interface Platform Design Document")[0] provide for OSPM in
0021 the device tree.
0022
0023 [0] https://developer.arm.com/documentation/den0056/latest
0024
0025 properties:
0026 $nodename:
0027 const: scmi
0028
0029 compatible:
0030 oneOf:
0031 - description: SCMI compliant firmware with mailbox transport
0032 items:
0033 - const: arm,scmi
0034 - description: SCMI compliant firmware with ARM SMC/HVC transport
0035 items:
0036 - const: arm,scmi-smc
0037 - description: SCMI compliant firmware with SCMI Virtio transport.
0038 The virtio transport only supports a single device.
0039 items:
0040 - const: arm,scmi-virtio
0041 - description: SCMI compliant firmware with OP-TEE transport
0042 items:
0043 - const: linaro,scmi-optee
0044
0045 interrupts:
0046 description:
0047 The interrupt that indicates message completion by the platform
0048 rather than by the return of the smc call. This should not be used
0049 except when the platform requires such behavior.
0050 maxItems: 1
0051
0052 interrupt-names:
0053 const: a2p
0054
0055 mbox-names:
0056 description:
0057 Specifies the mailboxes used to communicate with SCMI compliant
0058 firmware.
0059 items:
0060 - const: tx
0061 - const: rx
0062
0063 mboxes:
0064 description:
0065 List of phandle and mailbox channel specifiers. It should contain
0066 exactly one or two mailboxes, one for transmitting messages("tx")
0067 and another optional for receiving the notifications("rx") if supported.
0068 minItems: 1
0069 maxItems: 2
0070
0071 shmem:
0072 description:
0073 List of phandle pointing to the shared memory(SHM) area, for each
0074 transport channel specified.
0075 minItems: 1
0076 maxItems: 2
0077
0078 '#address-cells':
0079 const: 1
0080
0081 '#size-cells':
0082 const: 0
0083
0084 atomic-threshold-us:
0085 description:
0086 An optional time value, expressed in microseconds, representing, on this
0087 platform, the threshold above which any SCMI command, advertised to have
0088 an higher-than-threshold execution latency, should not be considered for
0089 atomic mode of operation, even if requested.
0090 default: 0
0091
0092 arm,smc-id:
0093 $ref: /schemas/types.yaml#/definitions/uint32
0094 description:
0095 SMC id required when using smc or hvc transports
0096
0097 linaro,optee-channel-id:
0098 $ref: /schemas/types.yaml#/definitions/uint32
0099 description:
0100 Channel specifier required when using OP-TEE transport.
0101
0102 protocol@11:
0103 type: object
0104 properties:
0105 reg:
0106 const: 0x11
0107
0108 '#power-domain-cells':
0109 const: 1
0110
0111 required:
0112 - '#power-domain-cells'
0113
0114 protocol@13:
0115 type: object
0116 properties:
0117 reg:
0118 const: 0x13
0119
0120 '#clock-cells':
0121 const: 1
0122
0123 required:
0124 - '#clock-cells'
0125
0126 protocol@14:
0127 type: object
0128 properties:
0129 reg:
0130 const: 0x14
0131
0132 '#clock-cells':
0133 const: 1
0134
0135 required:
0136 - '#clock-cells'
0137
0138 protocol@15:
0139 type: object
0140 properties:
0141 reg:
0142 const: 0x15
0143
0144 '#thermal-sensor-cells':
0145 const: 1
0146
0147 required:
0148 - '#thermal-sensor-cells'
0149
0150 protocol@16:
0151 type: object
0152 properties:
0153 reg:
0154 const: 0x16
0155
0156 '#reset-cells':
0157 const: 1
0158
0159 required:
0160 - '#reset-cells'
0161
0162 protocol@17:
0163 type: object
0164 properties:
0165 reg:
0166 const: 0x17
0167
0168 regulators:
0169 type: object
0170 description:
0171 The list of all regulators provided by this SCMI controller.
0172
0173 patternProperties:
0174 '^regulators@[0-9a-f]+$':
0175 type: object
0176 $ref: "../regulator/regulator.yaml#"
0177
0178 properties:
0179 reg:
0180 maxItems: 1
0181 description: Identifier for the voltage regulator.
0182
0183 required:
0184 - reg
0185
0186 protocol@18:
0187 type: object
0188 properties:
0189 reg:
0190 const: 0x18
0191
0192 additionalProperties: false
0193
0194 patternProperties:
0195 '^protocol@[0-9a-f]+$':
0196 type: object
0197 description:
0198 Each sub-node represents a protocol supported. If the platform
0199 supports a dedicated communication channel for a particular protocol,
0200 then the corresponding transport properties must be present.
0201 The virtio transport does not support a dedicated communication channel.
0202
0203 properties:
0204 reg:
0205 maxItems: 1
0206
0207 mbox-names:
0208 items:
0209 - const: tx
0210 - const: rx
0211
0212 mboxes:
0213 minItems: 1
0214 maxItems: 2
0215
0216 shmem:
0217 minItems: 1
0218 maxItems: 2
0219
0220 linaro,optee-channel-id:
0221 $ref: /schemas/types.yaml#/definitions/uint32
0222 description:
0223 Channel specifier required when using OP-TEE transport and
0224 protocol has a dedicated communication channel.
0225
0226 required:
0227 - reg
0228
0229 required:
0230 - compatible
0231
0232 if:
0233 properties:
0234 compatible:
0235 contains:
0236 const: arm,scmi
0237 then:
0238 properties:
0239 interrupts: false
0240 interrupt-names: false
0241
0242 required:
0243 - mboxes
0244 - shmem
0245
0246 else:
0247 if:
0248 properties:
0249 compatible:
0250 contains:
0251 const: arm,scmi-smc
0252 then:
0253 required:
0254 - arm,smc-id
0255 - shmem
0256
0257 else:
0258 if:
0259 properties:
0260 compatible:
0261 contains:
0262 const: linaro,scmi-optee
0263 then:
0264 required:
0265 - linaro,optee-channel-id
0266
0267 examples:
0268 - |
0269 firmware {
0270 scmi {
0271 compatible = "arm,scmi";
0272 mboxes = <&mhuB 0 0>,
0273 <&mhuB 0 1>;
0274 mbox-names = "tx", "rx";
0275 shmem = <&cpu_scp_lpri0>,
0276 <&cpu_scp_lpri1>;
0277
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280
0281 atomic-threshold-us = <10000>;
0282
0283 scmi_devpd: protocol@11 {
0284 reg = <0x11>;
0285 #power-domain-cells = <1>;
0286 };
0287
0288 scmi_dvfs: protocol@13 {
0289 reg = <0x13>;
0290 #clock-cells = <1>;
0291
0292 mboxes = <&mhuB 1 0>,
0293 <&mhuB 1 1>;
0294 mbox-names = "tx", "rx";
0295 shmem = <&cpu_scp_hpri0>,
0296 <&cpu_scp_hpri1>;
0297 };
0298
0299 scmi_clk: protocol@14 {
0300 reg = <0x14>;
0301 #clock-cells = <1>;
0302 };
0303
0304 scmi_sensors: protocol@15 {
0305 reg = <0x15>;
0306 #thermal-sensor-cells = <1>;
0307 };
0308
0309 scmi_reset: protocol@16 {
0310 reg = <0x16>;
0311 #reset-cells = <1>;
0312 };
0313
0314 scmi_voltage: protocol@17 {
0315 reg = <0x17>;
0316 regulators {
0317 #address-cells = <1>;
0318 #size-cells = <0>;
0319
0320 regulator_devX: regulator@0 {
0321 reg = <0x0>;
0322 regulator-max-microvolt = <3300000>;
0323 };
0324
0325 regulator_devY: regulator@9 {
0326 reg = <0x9>;
0327 regulator-min-microvolt = <500000>;
0328 regulator-max-microvolt = <4200000>;
0329 };
0330 };
0331 };
0332
0333 scmi_powercap: protocol@18 {
0334 reg = <0x18>;
0335 };
0336 };
0337 };
0338
0339 soc {
0340 #address-cells = <2>;
0341 #size-cells = <2>;
0342
0343 sram@50000000 {
0344 compatible = "mmio-sram";
0345 reg = <0x0 0x50000000 0x0 0x10000>;
0346
0347 #address-cells = <1>;
0348 #size-cells = <1>;
0349 ranges = <0 0x0 0x50000000 0x10000>;
0350
0351 cpu_scp_lpri0: scp-sram-section@0 {
0352 compatible = "arm,scmi-shmem";
0353 reg = <0x0 0x80>;
0354 };
0355
0356 cpu_scp_lpri1: scp-sram-section@80 {
0357 compatible = "arm,scmi-shmem";
0358 reg = <0x80 0x80>;
0359 };
0360
0361 cpu_scp_hpri0: scp-sram-section@100 {
0362 compatible = "arm,scmi-shmem";
0363 reg = <0x100 0x80>;
0364 };
0365
0366 cpu_scp_hpri2: scp-sram-section@180 {
0367 compatible = "arm,scmi-shmem";
0368 reg = <0x180 0x80>;
0369 };
0370 };
0371 };
0372
0373 - |
0374 firmware {
0375 scmi {
0376 compatible = "arm,scmi-smc";
0377 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
0378 arm,smc-id = <0xc3000001>;
0379
0380 #address-cells = <1>;
0381 #size-cells = <0>;
0382
0383 scmi_devpd1: protocol@11 {
0384 reg = <0x11>;
0385 #power-domain-cells = <1>;
0386 };
0387 };
0388 };
0389
0390 - |
0391 firmware {
0392 scmi {
0393 compatible = "linaro,scmi-optee";
0394 linaro,optee-channel-id = <0>;
0395
0396 #address-cells = <1>;
0397 #size-cells = <0>;
0398
0399 scmi_dvfs1: protocol@13 {
0400 reg = <0x13>;
0401 linaro,optee-channel-id = <1>;
0402 shmem = <&cpu_optee_lpri0>;
0403 #clock-cells = <1>;
0404 };
0405
0406 scmi_clk0: protocol@14 {
0407 reg = <0x14>;
0408 #clock-cells = <1>;
0409 };
0410 };
0411 };
0412
0413 soc {
0414 #address-cells = <2>;
0415 #size-cells = <2>;
0416
0417 sram@51000000 {
0418 compatible = "mmio-sram";
0419 reg = <0x0 0x51000000 0x0 0x10000>;
0420
0421 #address-cells = <1>;
0422 #size-cells = <1>;
0423 ranges = <0 0x0 0x51000000 0x10000>;
0424
0425 cpu_optee_lpri0: optee-sram-section@0 {
0426 compatible = "arm,scmi-shmem";
0427 reg = <0x0 0x80>;
0428 };
0429 };
0430 };
0431
0432 ...
