0001 Altera SoCFPGA ECC Manager
0002 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
0003 The ECC Manager counts and corrects single bit errors and counts/handles
0004 double bit errors which are uncorrectable.
0005
0006 Cyclone5 and Arria5 ECC Manager
0007 Required Properties:
0008 - compatible : Should be "altr,socfpga-ecc-manager"
0009 - #address-cells: must be 1
0010 - #size-cells: must be 1
0011 - ranges : standard definition, should translate from local addresses
0012
0013 Subcomponents:
0014
0015 L2 Cache ECC
0016 Required Properties:
0017 - compatible : Should be "altr,socfpga-l2-ecc"
0018 - reg : Address and size for ECC error interrupt clear registers.
0019 - interrupts : Should be single bit error interrupt, then double bit error
0020 interrupt. Note the rising edge type.
0021
0022 On Chip RAM ECC
0023 Required Properties:
0024 - compatible : Should be "altr,socfpga-ocram-ecc"
0025 - reg : Address and size for ECC error interrupt clear registers.
0026 - iram : phandle to On-Chip RAM definition.
0027 - interrupts : Should be single bit error interrupt, then double bit error
0028 interrupt. Note the rising edge type.
0029
0030 Example:
0031
0032 eccmgr: eccmgr@ffd08140 {
0033 compatible = "altr,socfpga-ecc-manager";
0034 #address-cells = <1>;
0035 #size-cells = <1>;
0036 ranges;
0037
0038 l2-ecc@ffd08140 {
0039 compatible = "altr,socfpga-l2-ecc";
0040 reg = <0xffd08140 0x4>;
0041 interrupts = <0 36 1>, <0 37 1>;
0042 };
0043
0044 ocram-ecc@ffd08144 {
0045 compatible = "altr,socfpga-ocram-ecc";
0046 reg = <0xffd08144 0x4>;
0047 iram = <&ocram>;
0048 interrupts = <0 178 1>, <0 179 1>;
0049 };
0050 };
0051
0052 Arria10 SoCFPGA ECC Manager
0053 The Arria10 SoC ECC Manager handles the IRQs for each peripheral
0054 in a shared register instead of individual IRQs like the Cyclone5
0055 and Arria5. Therefore the device tree is different as well.
0056
0057 Required Properties:
0058 - compatible : Should be "altr,socfpga-a10-ecc-manager"
0059 - altr,sysgr-syscon : phandle to Arria10 System Manager Block
0060 containing the ECC manager registers.
0061 - #address-cells: must be 1
0062 - #size-cells: must be 1
0063 - interrupts : Should be single bit error interrupt, then double bit error
0064 interrupt.
0065 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
0066 - #interrupt-cells : must be set to 2.
0067 - ranges : standard definition, should translate from local addresses
0068
0069 Subcomponents:
0070
0071 L2 Cache ECC
0072 Required Properties:
0073 - compatible : Should be "altr,socfpga-a10-l2-ecc"
0074 - reg : Address and size for ECC error interrupt clear registers.
0075 - interrupts : Should be single bit error interrupt, then double bit error
0076 interrupt, in this order.
0077
0078 On-Chip RAM ECC
0079 Required Properties:
0080 - compatible : Should be "altr,socfpga-a10-ocram-ecc"
0081 - reg : Address and size for ECC block registers.
0082 - interrupts : Should be single bit error interrupt, then double bit error
0083 interrupt, in this order.
0084
0085 Ethernet FIFO ECC
0086 Required Properties:
0087 - compatible : Should be "altr,socfpga-eth-mac-ecc"
0088 - reg : Address and size for ECC block registers.
0089 - altr,ecc-parent : phandle to parent Ethernet node.
0090 - interrupts : Should be single bit error interrupt, then double bit error
0091 interrupt, in this order.
0092
0093 NAND FIFO ECC
0094 Required Properties:
0095 - compatible : Should be "altr,socfpga-nand-ecc"
0096 - reg : Address and size for ECC block registers.
0097 - altr,ecc-parent : phandle to parent NAND node.
0098 - interrupts : Should be single bit error interrupt, then double bit error
0099 interrupt, in this order.
0100
0101 DMA FIFO ECC
0102 Required Properties:
0103 - compatible : Should be "altr,socfpga-dma-ecc"
0104 - reg : Address and size for ECC block registers.
0105 - altr,ecc-parent : phandle to parent DMA node.
0106 - interrupts : Should be single bit error interrupt, then double bit error
0107 interrupt, in this order.
0108
0109 USB FIFO ECC
0110 Required Properties:
0111 - compatible : Should be "altr,socfpga-usb-ecc"
0112 - reg : Address and size for ECC block registers.
0113 - altr,ecc-parent : phandle to parent USB node.
0114 - interrupts : Should be single bit error interrupt, then double bit error
0115 interrupt, in this order.
0116
0117 QSPI FIFO ECC
0118 Required Properties:
0119 - compatible : Should be "altr,socfpga-qspi-ecc"
0120 - reg : Address and size for ECC block registers.
0121 - altr,ecc-parent : phandle to parent QSPI node.
0122 - interrupts : Should be single bit error interrupt, then double bit error
0123 interrupt, in this order.
0124
0125 SDMMC FIFO ECC
0126 Required Properties:
0127 - compatible : Should be "altr,socfpga-sdmmc-ecc"
0128 - reg : Address and size for ECC block registers.
0129 - altr,ecc-parent : phandle to parent SD/MMC node.
0130 - interrupts : Should be single bit error interrupt, then double bit error
0131 interrupt, in this order for port A, and then single bit error interrupt,
0132 then double bit error interrupt in this order for port B.
0133
0134 Example:
0135
0136 eccmgr: eccmgr@ffd06000 {
0137 compatible = "altr,socfpga-a10-ecc-manager";
0138 altr,sysmgr-syscon = <&sysmgr>;
0139 #address-cells = <1>;
0140 #size-cells = <1>;
0141 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
0142 <0 0 IRQ_TYPE_LEVEL_HIGH>;
0143 interrupt-controller;
0144 #interrupt-cells = <2>;
0145 ranges;
0146
0147 l2-ecc@ffd06010 {
0148 compatible = "altr,socfpga-a10-l2-ecc";
0149 reg = <0xffd06010 0x4>;
0150 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
0151 <32 IRQ_TYPE_LEVEL_HIGH>;
0152 };
0153
0154 ocram-ecc@ff8c3000 {
0155 compatible = "altr,socfpga-a10-ocram-ecc";
0156 reg = <0xff8c3000 0x90>;
0157 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
0158 <33 IRQ_TYPE_LEVEL_HIGH> ;
0159 };
0160
0161 emac0-rx-ecc@ff8c0800 {
0162 compatible = "altr,socfpga-eth-mac-ecc";
0163 reg = <0xff8c0800 0x400>;
0164 altr,ecc-parent = <&gmac0>;
0165 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
0166 <36 IRQ_TYPE_LEVEL_HIGH>;
0167 };
0168
0169 emac0-tx-ecc@ff8c0c00 {
0170 compatible = "altr,socfpga-eth-mac-ecc";
0171 reg = <0xff8c0c00 0x400>;
0172 altr,ecc-parent = <&gmac0>;
0173 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
0174 <37 IRQ_TYPE_LEVEL_HIGH>;
0175 };
0176
0177 nand-buf-ecc@ff8c2000 {
0178 compatible = "altr,socfpga-nand-ecc";
0179 reg = <0xff8c2000 0x400>;
0180 altr,ecc-parent = <&nand>;
0181 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
0182 <43 IRQ_TYPE_LEVEL_HIGH>;
0183 };
0184
0185 nand-rd-ecc@ff8c2400 {
0186 compatible = "altr,socfpga-nand-ecc";
0187 reg = <0xff8c2400 0x400>;
0188 altr,ecc-parent = <&nand>;
0189 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
0190 <45 IRQ_TYPE_LEVEL_HIGH>;
0191 };
0192
0193 nand-wr-ecc@ff8c2800 {
0194 compatible = "altr,socfpga-nand-ecc";
0195 reg = <0xff8c2800 0x400>;
0196 altr,ecc-parent = <&nand>;
0197 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
0198 <44 IRQ_TYPE_LEVEL_HIGH>;
0199 };
0200
0201 dma-ecc@ff8c8000 {
0202 compatible = "altr,socfpga-dma-ecc";
0203 reg = <0xff8c8000 0x400>;
0204 altr,ecc-parent = <&pdma>;
0205 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
0206 <42 IRQ_TYPE_LEVEL_HIGH>;
0207
0208 usb0-ecc@ff8c8800 {
0209 compatible = "altr,socfpga-usb-ecc";
0210 reg = <0xff8c8800 0x400>;
0211 altr,ecc-parent = <&usb0>;
0212 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
0213 <34 IRQ_TYPE_LEVEL_HIGH>;
0214 };
0215
0216 qspi-ecc@ff8c8400 {
0217 compatible = "altr,socfpga-qspi-ecc";
0218 reg = <0xff8c8400 0x400>;
0219 altr,ecc-parent = <&qspi>;
0220 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
0221 <46 IRQ_TYPE_LEVEL_HIGH>;
0222 };
0223
0224 sdmmc-ecc@ff8c2c00 {
0225 compatible = "altr,socfpga-sdmmc-ecc";
0226 reg = <0xff8c2c00 0x400>;
0227 altr,ecc-parent = <&mmc>;
0228 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
0229 <47 IRQ_TYPE_LEVEL_HIGH>,
0230 <16 IRQ_TYPE_LEVEL_HIGH>,
0231 <48 IRQ_TYPE_LEVEL_HIGH>;
0232 };
0233 };
0234
0235 Stratix10 SoCFPGA ECC Manager (ARM64)
0236 The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
0237 in a shared register similar to the Arria10. However, Stratix10 ECC
0238 requires access to registers that can only be read from Secure Monitor
0239 with SMC calls. Therefore the device tree is slightly different. Note
0240 that only 1 interrupt is sent in Stratix10 because the double bit errors
0241 are treated as SErrors in ARM64 instead of IRQs in ARM32.
0242
0243 Required Properties:
0244 - compatible : Should be "altr,socfpga-s10-ecc-manager"
0245 - altr,sysgr-syscon : phandle to Stratix10 System Manager Block
0246 containing the ECC manager registers.
0247 - interrupts : Should be single bit error interrupt.
0248 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
0249 - #interrupt-cells : must be set to 2.
0250 - #address-cells: must be 1
0251 - #size-cells: must be 1
0252 - ranges : standard definition, should translate from local addresses
0253
0254 Subcomponents:
0255
0256 SDRAM ECC
0257 Required Properties:
0258 - compatible : Should be "altr,sdram-edac-s10"
0259 - interrupts : Should be single bit error interrupt.
0260
0261 On-Chip RAM ECC
0262 Required Properties:
0263 - compatible : Should be "altr,socfpga-s10-ocram-ecc"
0264 - reg : Address and size for ECC block registers.
0265 - altr,ecc-parent : phandle to parent OCRAM node.
0266 - interrupts : Should be single bit error interrupt.
0267
0268 Ethernet FIFO ECC
0269 Required Properties:
0270 - compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
0271 - reg : Address and size for ECC block registers.
0272 - altr,ecc-parent : phandle to parent Ethernet node.
0273 - interrupts : Should be single bit error interrupt.
0274
0275 NAND FIFO ECC
0276 Required Properties:
0277 - compatible : Should be "altr,socfpga-s10-nand-ecc"
0278 - reg : Address and size for ECC block registers.
0279 - altr,ecc-parent : phandle to parent NAND node.
0280 - interrupts : Should be single bit error interrupt.
0281
0282 DMA FIFO ECC
0283 Required Properties:
0284 - compatible : Should be "altr,socfpga-s10-dma-ecc"
0285 - reg : Address and size for ECC block registers.
0286 - altr,ecc-parent : phandle to parent DMA node.
0287 - interrupts : Should be single bit error interrupt.
0288
0289 USB FIFO ECC
0290 Required Properties:
0291 - compatible : Should be "altr,socfpga-s10-usb-ecc"
0292 - reg : Address and size for ECC block registers.
0293 - altr,ecc-parent : phandle to parent USB node.
0294 - interrupts : Should be single bit error interrupt.
0295
0296 SDMMC FIFO ECC
0297 Required Properties:
0298 - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
0299 - reg : Address and size for ECC block registers.
0300 - altr,ecc-parent : phandle to parent SD/MMC node.
0301 - interrupts : Should be single bit error interrupt for port A
0302 and then single bit error interrupt for port B.
0303
0304 Example:
0305
0306 eccmgr {
0307 compatible = "altr,socfpga-s10-ecc-manager";
0308 altr,sysmgr-syscon = <&sysmgr>;
0309 #address-cells = <1>;
0310 #size-cells = <1>;
0311 interrupts = <0 15 4>;
0312 interrupt-controller;
0313 #interrupt-cells = <2>;
0314 ranges;
0315
0316 sdramedac {
0317 compatible = "altr,sdram-edac-s10";
0318 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
0319 };
0320
0321 ocram-ecc@ff8cc000 {
0322 compatible = "altr,socfpga-s10-ocram-ecc";
0323 reg = <ff8cc000 0x100>;
0324 altr,ecc-parent = <&ocram>;
0325 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
0326 };
0327
0328 emac0-rx-ecc@ff8c0000 {
0329 compatible = "altr,socfpga-s10-eth-mac-ecc";
0330 reg = <0xff8c0000 0x100>;
0331 altr,ecc-parent = <&gmac0>;
0332 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0333 };
0334
0335 emac0-tx-ecc@ff8c0400 {
0336 compatible = "altr,socfpga-s10-eth-mac-ecc";
0337 reg = <0xff8c0400 0x100>;
0338 altr,ecc-parent = <&gmac0>;
0339 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
0340 };
0341
0342 nand-buf-ecc@ff8c8000 {
0343 compatible = "altr,socfpga-s10-nand-ecc";
0344 reg = <0xff8c8000 0x100>;
0345 altr,ecc-parent = <&nand>;
0346 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
0347 };
0348
0349 nand-rd-ecc@ff8c8400 {
0350 compatible = "altr,socfpga-s10-nand-ecc";
0351 reg = <0xff8c8400 0x100>;
0352 altr,ecc-parent = <&nand>;
0353 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
0354 };
0355
0356 nand-wr-ecc@ff8c8800 {
0357 compatible = "altr,socfpga-s10-nand-ecc";
0358 reg = <0xff8c8800 0x100>;
0359 altr,ecc-parent = <&nand>;
0360 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
0361 };
0362
0363 dma-ecc@ff8c9000 {
0364 compatible = "altr,socfpga-s10-dma-ecc";
0365 reg = <0xff8c9000 0x100>;
0366 altr,ecc-parent = <&pdma>;
0367 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
0368
0369 usb0-ecc@ff8c4000 {
0370 compatible = "altr,socfpga-s10-usb-ecc";
0371 reg = <0xff8c4000 0x100>;
0372 altr,ecc-parent = <&usb0>;
0373 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
0374 };
0375
0376 sdmmc-ecc@ff8c8c00 {
0377 compatible = "altr,socfpga-s10-sdmmc-ecc";
0378 reg = <0xff8c8c00 0x100>;
0379 altr,ecc-parent = <&mmc>;
0380 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
0381 <15 IRQ_TYPE_LEVEL_HIGH>;
0382 };
0383 };
