bindings/edac/dmc-520.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/edac/dmc-520.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM DMC-520 EDAC bindings
0008
0009 maintainers:
0010   - Lei Wang <lewan@microsoft.com>
0011
0012 description: |+
0013   DMC-520 node is defined to describe DRAM error detection and correction.
0014
0015   https://static.docs.arm.com/100000/0200/corelink_dmc520_trm_100000_0200_01_en.pdf
0016
0017 properties:
0018   compatible:
0019     items:
0020       - const: brcm,dmc-520
0021       - const: arm,dmc-520
0022
0023   reg:
0024     maxItems: 1
0025
0026   interrupts:
0027     minItems: 1
0028     maxItems: 10
0029
0030   interrupt-names:
0031     minItems: 1
0032     maxItems: 10
0033     items:
0034       enum:
0035         - ram_ecc_errc
0036         - ram_ecc_errd
0037         - dram_ecc_errc
0038         - dram_ecc_errd
0039         - failed_access
0040         - failed_prog
0041         - link_err
0042         - temperature_event
0043         - arch_fsm
0044         - phy_request
0045
0046 required:
0047   - compatible
0048   - reg
0049   - interrupts
0050   - interrupt-names
0051
0052 additionalProperties: false
0053
0054 examples:
0055   - |
0056     dmc0: dmc@200000 {
0057         compatible = "brcm,dmc-520", "arm,dmc-520";
0058         reg = <0x200000 0x80000>;
0059         interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
0060         interrupt-names = "dram_ecc_errc", "dram_ecc_errd";
0061     };