0001 * APM X-Gene SoC EDAC node
0002
0003 EDAC node is defined to describe on-chip error detection and correction.
0004 The follow error types are supported:
0005
0006 memory controller - Memory controller
0007 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
0008 L3 - L3 cache controller
0009 SoC - SoC IP's such as Ethernet, SATA, and etc
0010
0011 The following section describes the EDAC DT node binding.
0012
0013 Required properties:
0014 - compatible : Shall be "apm,xgene-edac".
0015 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
0016 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
0017 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
0018 - regmap-efuse : Regmap of the PMD efuse resource.
0019 - regmap-rb : Regmap of the register bus resource. This property
0020 is optional only for compatibility. If the RB
0021 error conditions are not cleared, it will
0022 continuously generate interrupt.
0023 - reg : First resource shall be the CPU bus (PCP) resource.
0024 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
0025 IRQ(s).
0026
0027 Required properties for memory controller subnode:
0028 - compatible : Shall be "apm,xgene-edac-mc".
0029 - reg : First resource shall be the memory controller unit
0030 (MCU) resource.
0031 - memory-controller : Instance number of the memory controller.
0032
0033 Required properties for PMD subnode:
0034 - compatible : Shall be "apm,xgene-edac-pmd" or
0035 "apm,xgene-edac-pmd-v2".
0036 - reg : First resource shall be the PMD resource.
0037 - pmd-controller : Instance number of the PMD controller.
0038
0039 Required properties for L3 subnode:
0040 - compatible : Shall be "apm,xgene-edac-l3" or
0041 "apm,xgene-edac-l3-v2".
0042 - reg : First resource shall be the L3 EDAC resource.
0043
0044 Required properties for SoC subnode:
0045 - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
0046 "apm,xgene-edac-l3-soc" for general value reporting
0047 only.
0048 - reg : First resource shall be the SoC EDAC resource.
0049
0050 Example:
0051 csw: csw@7e200000 {
0052 compatible = "apm,xgene-csw", "syscon";
0053 reg = <0x0 0x7e200000 0x0 0x1000>;
0054 };
0055
0056 mcba: mcba@7e700000 {
0057 compatible = "apm,xgene-mcb", "syscon";
0058 reg = <0x0 0x7e700000 0x0 0x1000>;
0059 };
0060
0061 mcbb: mcbb@7e720000 {
0062 compatible = "apm,xgene-mcb", "syscon";
0063 reg = <0x0 0x7e720000 0x0 0x1000>;
0064 };
0065
0066 efuse: efuse@1054a000 {
0067 compatible = "apm,xgene-efuse", "syscon";
0068 reg = <0x0 0x1054a000 0x0 0x20>;
0069 };
0070
0071 rb: rb@7e000000 {
0072 compatible = "apm,xgene-rb", "syscon";
0073 reg = <0x0 0x7e000000 0x0 0x10>;
0074 };
0075
0076 edac@78800000 {
0077 compatible = "apm,xgene-edac";
0078 #address-cells = <2>;
0079 #size-cells = <2>;
0080 ranges;
0081 regmap-csw = <&csw>;
0082 regmap-mcba = <&mcba>;
0083 regmap-mcbb = <&mcbb>;
0084 regmap-efuse = <&efuse>;
0085 regmap-rb = <&rb>;
0086 reg = <0x0 0x78800000 0x0 0x100>;
0087 interrupts = <0x0 0x20 0x4>,
0088 <0x0 0x21 0x4>,
0089 <0x0 0x27 0x4>;
0090
0091 edacmc@7e800000 {
0092 compatible = "apm,xgene-edac-mc";
0093 reg = <0x0 0x7e800000 0x0 0x1000>;
0094 memory-controller = <0>;
0095 };
0096
0097 edacpmd@7c000000 {
0098 compatible = "apm,xgene-edac-pmd";
0099 reg = <0x0 0x7c000000 0x0 0x200000>;
0100 pmd-controller = <0>;
0101 };
0102
0103 edacl3@7e600000 {
0104 compatible = "apm,xgene-edac-l3";
0105 reg = <0x0 0x7e600000 0x0 0x1000>;
0106 };
0107
0108 edacsoc@7e930000 {
0109 compatible = "apm,xgene-edac-soc-v1";
0110 reg = <0x0 0x7e930000 0x0 0x1000>;
0111 };
0112 };
