0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mediatek mt8195 DSP core
0008
0009 maintainers:
0010 - YC Hung <yc.hung@mediatek.com>
0011
0012 description: |
0013 Some boards from mt8195 contain a DSP core used for
0014 advanced pre- and post- audio processing.
0015
0016 properties:
0017 compatible:
0018 const: mediatek,mt8195-dsp
0019
0020 reg:
0021 items:
0022 - description: Address and size of the DSP Cfg registers
0023 - description: Address and size of the DSP SRAM
0024
0025 reg-names:
0026 items:
0027 - const: cfg
0028 - const: sram
0029
0030 clocks:
0031 items:
0032 - description: mux for audio dsp clock
0033 - description: 26M clock
0034 - description: mux for audio dsp local bus
0035 - description: default audio dsp local bus clock source
0036 - description: clock gate for audio dsp clock
0037 - description: mux for audio dsp access external bus
0038
0039 clock-names:
0040 items:
0041 - const: adsp_sel
0042 - const: clk26m_ck
0043 - const: audio_local_bus
0044 - const: mainpll_d7_d2
0045 - const: scp_adsp_audiodsp
0046 - const: audio_h
0047
0048 power-domains:
0049 maxItems: 1
0050
0051 mboxes:
0052 items:
0053 - description: mailbox for receiving audio DSP requests.
0054 - description: mailbox for transmitting requests to audio DSP.
0055
0056 mbox-names:
0057 items:
0058 - const: rx
0059 - const: tx
0060
0061 memory-region:
0062 items:
0063 - description: dma buffer between host and DSP.
0064 - description: DSP system memory.
0065
0066 required:
0067 - compatible
0068 - reg
0069 - reg-names
0070 - clocks
0071 - clock-names
0072 - memory-region
0073 - power-domains
0074 - mbox-names
0075 - mboxes
0076
0077 additionalProperties: false
0078
0079 examples:
0080 - |
0081 #include <dt-bindings/interrupt-controller/arm-gic.h>
0082 #include <dt-bindings/interrupt-controller/irq.h>
0083 dsp@10803000 {
0084 compatible = "mediatek,mt8195-dsp";
0085 reg = <0x10803000 0x1000>,
0086 <0x10840000 0x40000>;
0087 reg-names = "cfg", "sram";
0088 clocks = <&topckgen 10>, //CLK_TOP_ADSP
0089 <&clk26m>,
0090 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
0091 <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
0092 <&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
0093 <&topckgen 34>; //CLK_TOP_AUDIO_H
0094 clock-names = "adsp_sel",
0095 "clk26m_ck",
0096 "audio_local_bus",
0097 "mainpll_d7_d2",
0098 "scp_adsp_audiodsp",
0099 "audio_h";
0100 memory-region = <&adsp_dma_mem_reserved>,
0101 <&adsp_mem_reserved>;
0102 power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
0103 mbox-names = "rx", "tx";
0104 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
0105 };