0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8 DSP core
0008
0009 maintainers:
0010 - Daniel Baluta <daniel.baluta@nxp.com>
0011 - Shengjiu Wang <shengjiu.wang@nxp.com>
0012
0013 description: |
0014 Some boards from i.MX8 family contain a DSP core used for
0015 advanced pre- and post- audio processing.
0016
0017 properties:
0018 compatible:
0019 enum:
0020 - fsl,imx8qxp-dsp
0021 - fsl,imx8qm-dsp
0022 - fsl,imx8mp-dsp
0023 - fsl,imx8qxp-hifi4
0024 - fsl,imx8qm-hifi4
0025 - fsl,imx8mp-hifi4
0026 - fsl,imx8ulp-hifi4
0027
0028 reg:
0029 maxItems: 1
0030
0031 clocks:
0032 items:
0033 - description: ipg clock
0034 - description: ocram clock
0035 - description: core clock
0036 - description: debug interface clock
0037 - description: message unit clock
0038 minItems: 3
0039
0040 clock-names:
0041 items:
0042 - const: ipg
0043 - const: ocram
0044 - const: core
0045 - const: debug
0046 - const: mu
0047 minItems: 3
0048
0049 power-domains:
0050 description:
0051 List of phandle and PM domain specifier as documented in
0052 Documentation/devicetree/bindings/power/power_domain.txt
0053 minItems: 1
0054 maxItems: 4
0055
0056 mboxes:
0057 description:
0058 List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
0059 or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
0060 (see mailbox/fsl,mu.txt)
0061 minItems: 3
0062 maxItems: 4
0063
0064 mbox-names:
0065 minItems: 3
0066 maxItems: 4
0067
0068 memory-region:
0069 description:
0070 phandle to a node describing reserved memory (System RAM memory)
0071 used by DSP (see bindings/reserved-memory/reserved-memory.txt)
0072 minItems: 1
0073 maxItems: 4
0074
0075 firmware-name:
0076 description: |
0077 Default name of the firmware to load to the remote processor.
0078
0079 fsl,dsp-ctrl:
0080 $ref: /schemas/types.yaml#/definitions/phandle
0081 description:
0082 Phandle to syscon block which provide access for processor enablement
0083
0084 required:
0085 - compatible
0086 - reg
0087 - clocks
0088 - clock-names
0089 - power-domains
0090 - mboxes
0091 - mbox-names
0092 - memory-region
0093
0094 allOf:
0095 - if:
0096 properties:
0097 compatible:
0098 contains:
0099 enum:
0100 - fsl,imx8qxp-dsp
0101 - fsl,imx8qm-dsp
0102 - fsl,imx8qxp-hifi4
0103 - fsl,imx8qm-hifi4
0104 then:
0105 properties:
0106 power-domains:
0107 minItems: 4
0108 else:
0109 properties:
0110 power-domains:
0111 maxItems: 1
0112
0113 - if:
0114 properties:
0115 compatible:
0116 contains:
0117 enum:
0118 - fsl,imx8qxp-hifi4
0119 - fsl,imx8qm-hifi4
0120 - fsl,imx8mp-hifi4
0121 - fsl,imx8ulp-hifi4
0122 then:
0123 properties:
0124 memory-region:
0125 minItems: 4
0126 mboxes:
0127 maxItems: 3
0128 mbox-names:
0129 items:
0130 - const: tx
0131 - const: rx
0132 - const: rxdb
0133 else:
0134 properties:
0135 memory-region:
0136 maxItems: 1
0137 mboxes:
0138 minItems: 4
0139 mbox-names:
0140 items:
0141 - const: txdb0
0142 - const: txdb1
0143 - const: rxdb0
0144 - const: rxdb1
0145
0146 additionalProperties: false
0147
0148 examples:
0149 - |
0150 #include <dt-bindings/firmware/imx/rsrc.h>
0151 #include <dt-bindings/clock/imx8-clock.h>
0152 dsp@596e8000 {
0153 compatible = "fsl,imx8qxp-dsp";
0154 reg = <0x596e8000 0x88000>;
0155 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
0156 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
0157 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
0158 clock-names = "ipg", "ocram", "core";
0159 power-domains = <&pd IMX_SC_R_MU_13A>,
0160 <&pd IMX_SC_R_MU_13B>,
0161 <&pd IMX_SC_R_DSP>,
0162 <&pd IMX_SC_R_DSP_RAM>;
0163 mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
0164 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
0165 memory-region = <&dsp_reserved>;
0166 };
0167 - |
0168 #include <dt-bindings/clock/imx8mp-clock.h>
0169 dsp_reserved: dsp@92400000 {
0170 reg = <0x92400000 0x1000000>;
0171 no-map;
0172 };
0173 dsp_vdev0vring0: vdev0vring0@942f0000 {
0174 reg = <0x942f0000 0x8000>;
0175 no-map;
0176 };
0177 dsp_vdev0vring1: vdev0vring1@942f8000 {
0178 reg = <0x942f8000 0x8000>;
0179 no-map;
0180 };
0181 dsp_vdev0buffer: vdev0buffer@94300000 {
0182 compatible = "shared-dma-pool";
0183 reg = <0x94300000 0x100000>;
0184 no-map;
0185 };
0186
0187 dsp: dsp@3b6e8000 {
0188 compatible = "fsl,imx8mp-hifi4";
0189 reg = <0x3b6e8000 0x88000>;
0190 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
0191 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
0192 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
0193 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
0194 clock-names = "ipg", "ocram", "core", "debug";
0195 firmware-name = "imx/dsp/hifi4.bin";
0196 power-domains = <&audiomix_pd>;
0197 mbox-names = "tx", "rx", "rxdb";
0198 mboxes = <&mu2 0 0>,
0199 <&mu2 1 0>,
0200 <&mu2 3 0>;
0201 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
0202 <&dsp_vdev0vring1>, <&dsp_reserved>;
0203 fsl,dsp-ctrl = <&audio_blk_ctrl>;
0204 };
