0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
0008
0009 description: |
0010 These bindings describe the DMA engine included in the Xilinx ZynqMP
0011 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
0012 channels for a video stream, 1 channel for a graphics stream, and 2 channels
0013 for an audio stream).
0014
0015 maintainers:
0016 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0017
0018 allOf:
0019 - $ref: "../dma-controller.yaml#"
0020
0021 properties:
0022 "#dma-cells":
0023 const: 1
0024 description: |
0025 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
0026 for a list of channel IDs).
0027
0028 compatible:
0029 const: xlnx,zynqmp-dpdma
0030
0031 reg:
0032 maxItems: 1
0033
0034 interrupts:
0035 maxItems: 1
0036
0037 clocks:
0038 description: The AXI clock
0039 maxItems: 1
0040
0041 clock-names:
0042 const: axi_clk
0043
0044 required:
0045 - "#dma-cells"
0046 - compatible
0047 - reg
0048 - interrupts
0049 - clocks
0050 - clock-names
0051
0052 additionalProperties: false
0053
0054 examples:
0055 - |
0056 #include <dt-bindings/interrupt-controller/arm-gic.h>
0057
0058 dma: dma-controller@fd4c0000 {
0059 compatible = "xlnx,zynqmp-dpdma";
0060 reg = <0xfd4c0000 0x1000>;
0061 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0062 interrupt-parent = <&gic>;
0063 clocks = <&dpdma_clk>;
0064 clock-names = "axi_clk";
0065 #dma-cells = <1>;
0066 };
0067
0068 ...
