0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx ZynqMP DMA Engine
0008
0009 description: |
0010 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
0011 memory to device and device to memory transfers. It also has flow
0012 control and rate control support for slave/peripheral dma access.
0013
0014 maintainers:
0015 - Michael Tretter <m.tretter@pengutronix.de>
0016
0017 allOf:
0018 - $ref: "../dma-controller.yaml#"
0019
0020 properties:
0021 "#dma-cells":
0022 const: 1
0023
0024 compatible:
0025 const: xlnx,zynqmp-dma-1.0
0026
0027 reg:
0028 description: memory map for gdma/adma module access
0029 maxItems: 1
0030
0031 interrupts:
0032 description: DMA channel interrupt
0033 maxItems: 1
0034
0035 clocks:
0036 description: input clocks
0037 minItems: 2
0038 maxItems: 2
0039
0040 clock-names:
0041 items:
0042 - const: clk_main
0043 - const: clk_apb
0044
0045 xlnx,bus-width:
0046 $ref: /schemas/types.yaml#/definitions/uint32
0047 enum:
0048 - 64
0049 - 128
0050 description: AXI bus width in bits
0051
0052 iommus:
0053 maxItems: 1
0054
0055 power-domains:
0056 maxItems: 1
0057
0058 dma-coherent:
0059 description: present if dma operations are coherent
0060
0061 required:
0062 - "#dma-cells"
0063 - compatible
0064 - reg
0065 - interrupts
0066 - clocks
0067 - clock-names
0068
0069 additionalProperties: false
0070
0071 examples:
0072 - |
0073 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
0074
0075 fpd_dma_chan1: dma-controller@fd500000 {
0076 compatible = "xlnx,zynqmp-dma-1.0";
0077 reg = <0xfd500000 0x1000>;
0078 interrupt-parent = <&gic>;
0079 interrupts = <0 117 0x4>;
0080 #dma-cells = <1>;
0081 clock-names = "clk_main", "clk_apb";
0082 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
0083 xlnx,bus-width = <128>;
0084 dma-coherent;
0085 };
