0001 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
0002 It can be configured to have one channel or two channels. If configured
0003 as two channels, one is to transmit to the video device and another is
0004 to receive from the video device.
0005
0006 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
0007 target devices. It can be configured to have one channel or two channels.
0008 If configured as two channels, one is to transmit to the device and another
0009 is to receive from the device.
0010
0011 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
0012 address and a memory-mapped destination address.
0013
0014 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
0015 target devices. It can be configured to have up to 16 independent transmit
0016 and receive channels.
0017
0018 Required properties:
0019 - compatible: Should be one of-
0020 "xlnx,axi-vdma-1.00.a"
0021 "xlnx,axi-dma-1.00.a"
0022 "xlnx,axi-cdma-1.00.a"
0023 "xlnx,axi-mcdma-1.00.a"
0024 - #dma-cells: Should be <1>, see "dmas" property below
0025 - reg: Should contain VDMA registers location and length.
0026 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
0027 - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
0028 - dma-channel child node: Should have at least one channel and can have up to
0029 two channels per device. This node specifies the properties of each
0030 DMA channel (see child node properties below).
0031 - clocks: Input clock specifier. Refer to common clock bindings.
0032 - clock-names: List of input clocks
0033 For VDMA:
0034 Required elements: "s_axi_lite_aclk"
0035 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
0036 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
0037 For CDMA:
0038 Required elements: "s_axi_lite_aclk", "m_axi_aclk"
0039 For AXIDMA and MCDMA:
0040 Required elements: "s_axi_lite_aclk"
0041 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
0042 "m_axi_sg_aclk"
0043
0044 Required properties for VDMA:
0045 - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
0046
0047 Optional properties for AXI DMA and MCDMA:
0048 - xlnx,sg-length-width: Should be set to the width in bits of the length
0049 register as configured in h/w. Takes values {8...26}. If the property
0050 is missing or invalid then the default value 23 is used. This is the
0051 maximum value that is supported by all IP versions.
0052 Optional properties for VDMA:
0053 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
0054 It takes following values:
0055 {1}, flush both channels
0056 {2}, flush mm2s channel
0057 {3}, flush s2mm channel
0058
0059 Required child node properties:
0060 - compatible:
0061 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
0062 "xlnx,axi-vdma-s2mm-channel".
0063 For CDMA: It should be "xlnx,axi-cdma-channel".
0064 For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
0065 or "xlnx,axi-dma-s2mm-channel".
0066 - interrupts: Should contain per channel VDMA interrupts.
0067 - xlnx,datawidth: Should contain the stream data width, take values
0068 {32,64...1024}.
0069
0070 Optional child node properties:
0071 - xlnx,include-dre: Tells hardware is configured for Data
0072 Realignment Engine.
0073 Optional child node properties for VDMA:
0074 - xlnx,genlock-mode: Tells Genlock synchronization is
0075 enabled/disabled in hardware.
0076 - xlnx,enable-vert-flip: Tells vertical flip is
0077 enabled/disabled in hardware(S2MM path).
0078 Optional child node properties for MCDMA:
0079 - dma-channels: Number of dma channels in child node.
0080
0081 Example:
0082 ++++++++
0083
0084 axi_vdma_0: axivdma@40030000 {
0085 compatible = "xlnx,axi-vdma-1.00.a";
0086 #dma_cells = <1>;
0087 reg = < 0x40030000 0x10000 >;
0088 dma-ranges = <0x00000000 0x00000000 0x40000000>;
0089 xlnx,num-fstores = <0x8>;
0090 xlnx,flush-fsync = <0x1>;
0091 xlnx,addrwidth = <0x20>;
0092 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
0093 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
0094 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
0095 dma-channel@40030000 {
0096 compatible = "xlnx,axi-vdma-mm2s-channel";
0097 interrupts = < 0 54 4 >;
0098 xlnx,datawidth = <0x40>;
0099 } ;
0100 dma-channel@40030030 {
0101 compatible = "xlnx,axi-vdma-s2mm-channel";
0102 interrupts = < 0 53 4 >;
0103 xlnx,datawidth = <0x40>;
0104 } ;
0105 } ;
0106
0107
0108 * DMA client
0109
0110 Required properties:
0111 - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
0112 where Channel ID is '0' for write/tx and '1' for read/rx
0113 channel. For MCMDA, MM2S channel(write/tx) ID start from
0114 '0' and is in [0-15] range. S2MM channel(read/rx) ID start
0115 from '16' and is in [16-31] range. These channels ID are
0116 fixed irrespective of IP configuration.
0117
0118 - dma-names: a list of DMA channel names, one per "dmas" entry
0119
0120 Example:
0121 ++++++++
0122
0123 vdmatest_0: vdmatest@0 {
0124 compatible ="xlnx,axi-vdma-test-1.00.a";
0125 dmas = <&axi_vdma_0 0
0126 &axi_vdma_0 1>;
0127 dma-names = "vdma0", "vdma1";
0128 } ;
