0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2019 Texas Instruments Incorporated
0003 # Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0004 %YAML 1.2
0005 ---
0006 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
0007 $schema: http://devicetree.org/meta-schemas/core.yaml#
0008
0009 title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
0010
0011 maintainers:
0012 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
0013
0014 description: |
0015 The UDMA-P is intended to perform similar (but significantly upgraded)
0016 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
0017 module supports the transmission and reception of various packet types.
0018 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
0019 data structure compliant packets to/from smaller data blocks that are natively
0020 compatible with the specific requirements of each connected peripheral.
0021 Multiple Tx and Rx channels are provided within the DMA which allow multiple
0022 segmentation or reassembly operations to be ongoing. The DMA controller
0023 maintains state information for each of the channels which allows packet
0024 segmentation and reassembly operations to be time division multiplexed between
0025 channels in order to share the underlying DMA hardware. An external DMA
0026 scheduler is used to control the ordering and rate at which this multiplexing
0027 occurs for Transmit operations. The ordering and rate of Receive operations
0028 is indirectly controlled by the order in which blocks are pushed into the DMA
0029 on the Rx PSI-L interface.
0030
0031 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
0032 channels. Channels in the UDMA-P can be configured to be either Packet-Based
0033 or Third-Party channels on a channel by channel basis.
0034
0035 All transfers within NAVSS is done between PSI-L source and destination
0036 threads.
0037 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
0038 legacy, non PSI-L native peripherals. In the later case a special, small PDMA
0039 is tasked to act as a bridge between the PSI-L fabric and the legacy
0040 peripheral.
0041
0042 PDMAs can be configured via UDMAP peer registers to match with the
0043 configuration of the legacy peripheral.
0044
0045 allOf:
0046 - $ref: "../dma-controller.yaml#"
0047
0048 properties:
0049 "#dma-cells":
0050 minimum: 1
0051 maximum: 2
0052 description: |
0053 The cell is the PSI-L thread ID of the remote (to UDMAP) end.
0054 Valid ranges for thread ID depends on the data movement direction:
0055 for source thread IDs (rx): 0 - 0x7fff
0056 for destination thread IDs (tx): 0x8000 - 0xffff
0057
0058 Please refer to the device documentation for the PSI-L thread map and also
0059 the PSI-L peripheral chapter for the correct thread ID.
0060
0061 When #dma-cells is 2, the second parameter is the channel ATYPE.
0062
0063 compatible:
0064 enum:
0065 - ti,am654-navss-main-udmap
0066 - ti,am654-navss-mcu-udmap
0067 - ti,j721e-navss-main-udmap
0068 - ti,j721e-navss-mcu-udmap
0069
0070 reg:
0071 maxItems: 3
0072
0073 reg-names:
0074 items:
0075 - const: gcfg
0076 - const: rchanrt
0077 - const: tchanrt
0078
0079 msi-parent: true
0080
0081 ti,sci:
0082 description: phandle to TI-SCI compatible System controller node
0083 $ref: /schemas/types.yaml#/definitions/phandle
0084
0085 ti,sci-dev-id:
0086 description: TI-SCI device id of UDMAP
0087 $ref: /schemas/types.yaml#/definitions/uint32
0088
0089 ti,ringacc:
0090 description: phandle to the ring accelerator node
0091 $ref: /schemas/types.yaml#/definitions/phandle
0092
0093 ti,sci-rm-range-tchan:
0094 description: |
0095 Array of UDMA tchan resource subtypes for resource allocation for this
0096 host
0097 $ref: /schemas/types.yaml#/definitions/uint32-array
0098 minItems: 1
0099 # Should be enough
0100 maxItems: 255
0101
0102 ti,sci-rm-range-rchan:
0103 description: |
0104 Array of UDMA rchan resource subtypes for resource allocation for this
0105 host
0106 $ref: /schemas/types.yaml#/definitions/uint32-array
0107 minItems: 1
0108 # Should be enough
0109 maxItems: 255
0110
0111 ti,sci-rm-range-rflow:
0112 description: |
0113 Array of UDMA rflow resource subtypes for resource allocation for this
0114 host
0115 $ref: /schemas/types.yaml#/definitions/uint32-array
0116 minItems: 1
0117 # Should be enough
0118 maxItems: 255
0119
0120 required:
0121 - compatible
0122 - "#dma-cells"
0123 - reg
0124 - reg-names
0125 - msi-parent
0126 - ti,sci
0127 - ti,sci-dev-id
0128 - ti,ringacc
0129 - ti,sci-rm-range-tchan
0130 - ti,sci-rm-range-rchan
0131 - ti,sci-rm-range-rflow
0132
0133 if:
0134 properties:
0135 "#dma-cells":
0136 const: 2
0137 then:
0138 properties:
0139 ti,udma-atype:
0140 description: ATYPE value which should be used by non slave channels
0141 $ref: /schemas/types.yaml#/definitions/uint32
0142
0143 required:
0144 - ti,udma-atype
0145
0146 unevaluatedProperties: false
0147
0148 examples:
0149 - |+
0150 cbass_main {
0151 #address-cells = <2>;
0152 #size-cells = <2>;
0153
0154 cbass_main_navss: navss@30800000 {
0155 compatible = "simple-mfd";
0156 #address-cells = <2>;
0157 #size-cells = <2>;
0158 dma-coherent;
0159 dma-ranges;
0160 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
0161
0162 ti,sci-dev-id = <118>;
0163
0164 main_udmap: dma-controller@31150000 {
0165 compatible = "ti,am654-navss-main-udmap";
0166 reg = <0x0 0x31150000 0x0 0x100>,
0167 <0x0 0x34000000 0x0 0x100000>,
0168 <0x0 0x35000000 0x0 0x100000>;
0169 reg-names = "gcfg", "rchanrt", "tchanrt";
0170 #dma-cells = <1>;
0171
0172 ti,ringacc = <&ringacc>;
0173
0174 msi-parent = <&inta_main_udmass>;
0175
0176 ti,sci = <&dmsc>;
0177 ti,sci-dev-id = <188>;
0178
0179 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
0180 <0x2>; /* TX_CHAN */
0181 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
0182 <0x5>; /* RX_CHAN */
0183 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
0184 };
0185 };
0186 };
