0001 Texas Instruments eDMA
0002
0003 The eDMA3 consists of two components: Channel controller (CC) and Transfer
0004 Controller(s) (TC). The CC is the main entry for DMA users since it is
0005 responsible for the DMA channel handling, while the TCs are responsible to
0006 execute the actual DMA tansfer.
0007
0008 ------------------------------------------------------------------------------
0009 eDMA3 Channel Controller
0010
0011 Required properties:
0012 --------------------
0013 - compatible: Should be:
0014 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
0015 AM33xx and AM43xx SoCs.
0016 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
0017 channel controller(s) on 66AK2G.
0018 - #dma-cells: Should be set to <2>. The first number is the DMA request
0019 number and the second is the TC the channel is serviced on.
0020 - reg: Memory map of eDMA CC
0021 - reg-names: "edma3_cc"
0022 - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
0023 - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
0024 - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
0025 <&tptc_phandle TC_priority_number>. The highest priority is 0.
0026
0027 SoC-specific Required properties:
0028 --------------------------------
0029 The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
0030 - ti,hwmods: Name of the hwmods associated to the eDMA CC.
0031
0032 The following are mandatory properties for 66AK2G SoCs only:
0033 - power-domains:Should contain a phandle to a PM domain provider node
0034 and an args specifier containing the device id
0035 value. This property is as per the binding,
0036 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
0037
0038 Optional properties:
0039 -------------------
0040 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
0041 these channels will be SW triggered channels. See example.
0042 - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
0043 the driver, they are allocated to be used by for example the
0044 DSP. See example.
0045 - dma-channel-mask: Mask of usable channels.
0046 Single uint32 for EDMA with 32 channels, array of two uint32 for
0047 EDMA with 64 channels. See example and
0048 Documentation/devicetree/bindings/dma/dma-common.yaml
0049
0050
0051 ------------------------------------------------------------------------------
0052 eDMA3 Transfer Controller
0053
0054 Required properties:
0055 --------------------
0056 - compatible: Should be:
0057 - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
0058 AM33xx and AM43xx SoCs.
0059 - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
0060 transfer controller(s) on 66AK2G.
0061 - reg: Memory map of eDMA TC
0062 - interrupts: Interrupt number for TCerrint.
0063
0064 SoC-specific Required properties:
0065 --------------------------------
0066 The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
0067 - ti,hwmods: Name of the hwmods associated to the eDMA TC.
0068
0069 The following are mandatory properties for 66AK2G SoCs only:
0070 - power-domains:Should contain a phandle to a PM domain provider node
0071 and an args specifier containing the device id
0072 value. This property is as per the binding,
0073 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
0074
0075 Optional properties:
0076 -------------------
0077 - interrupt-names: "edma3_tcerrint"
0078
0079 ------------------------------------------------------------------------------
0080 Examples:
0081
0082 1.
0083 edma: edma@49000000 {
0084 compatible = "ti,edma3-tpcc";
0085 ti,hwmods = "tpcc";
0086 reg = <0x49000000 0x10000>;
0087 reg-names = "edma3_cc";
0088 interrupts = <12 13 14>;
0089 interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
0090 dma-requests = <64>;
0091 #dma-cells = <2>;
0092
0093 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
0094
0095 /* Channel 20 and 21 is allocated for memcpy */
0096 ti,edma-memcpy-channels = <20 21>;
0097 /* The following PaRAM slots are reserved: 35-44 and 100-109 */
0098 ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
0099 /* The following channels are reserved: 35-44 */
0100 dma-channel-mask = <0xffffffff /* Channel 0-31 */
0101 0xffffe007>; /* Channel 32-63 */
0102 };
0103
0104 edma_tptc0: tptc@49800000 {
0105 compatible = "ti,edma3-tptc";
0106 ti,hwmods = "tptc0";
0107 reg = <0x49800000 0x100000>;
0108 interrupts = <112>;
0109 interrupt-names = "edm3_tcerrint";
0110 };
0111
0112 edma_tptc1: tptc@49900000 {
0113 compatible = "ti,edma3-tptc";
0114 ti,hwmods = "tptc1";
0115 reg = <0x49900000 0x100000>;
0116 interrupts = <113>;
0117 interrupt-names = "edm3_tcerrint";
0118 };
0119
0120 edma_tptc2: tptc@49a00000 {
0121 compatible = "ti,edma3-tptc";
0122 ti,hwmods = "tptc2";
0123 reg = <0x49a00000 0x100000>;
0124 interrupts = <114>;
0125 interrupt-names = "edm3_tcerrint";
0126 };
0127
0128 sham: sham@53100000 {
0129 compatible = "ti,omap4-sham";
0130 ti,hwmods = "sham";
0131 reg = <0x53100000 0x200>;
0132 interrupts = <109>;
0133 /* DMA channel 36 executed on eDMA TC0 - low priority queue */
0134 dmas = <&edma 36 0>;
0135 dma-names = "rx";
0136 };
0137
0138 mcasp0: mcasp@48038000 {
0139 compatible = "ti,am33xx-mcasp-audio";
0140 ti,hwmods = "mcasp0";
0141 reg = <0x48038000 0x2000>,
0142 <0x46000000 0x400000>;
0143 reg-names = "mpu", "dat";
0144 interrupts = <80>, <81>;
0145 interrupt-names = "tx", "rx";
0146 /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
0147 dmas = <&edma 8 2>,
0148 <&edma 9 2>;
0149 dma-names = "tx", "rx";
0150 };
0151
0152 2.
0153 edma1: edma@2728000 {
0154 compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
0155 reg = <0x02728000 0x8000>;
0156 reg-names = "edma3_cc";
0157 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
0158 <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
0159 <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
0160 interrupt-names = "edma3_ccint", "emda3_mperr",
0161 "edma3_ccerrint";
0162 dma-requests = <64>;
0163 #dma-cells = <2>;
0164
0165 ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
0166
0167 /*
0168 * memcpy is disabled, can be enabled with:
0169 * ti,edma-memcpy-channels = <12 13 14 15>;
0170 * for example.
0171 */
0172
0173 power-domains = <&k2g_pds 0x4f>;
0174 };
0175
0176 edma1_tptc0: tptc@27b0000 {
0177 compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
0178 reg = <0x027b0000 0x400>;
0179 power-domains = <&k2g_pds 0x4f>;
0180 };
0181
0182 edma1_tptc1: tptc@27b8000 {
0183 compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
0184 reg = <0x027b8000 0x400>;
0185 power-domains = <&k2g_pds 0x4f>;
0186 };
0187
0188 mmc0: mmc@23000000 {
0189 compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
0190 reg = <0x23000000 0x400>;
0191 interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
0192 dmas = <&edma1 24 0>, <&edma1 25 0>;
0193 dma-names = "tx", "rx";
0194 bus-width = <4>;
0195 ti,needs-special-reset;
0196 no-1-8-v;
0197 max-frequency = <96000000>;
0198 power-domains = <&k2g_pds 0xb>;
0199 clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
0200 clock-names = "fck", "mmchsdb_fck";
0201 };
0202
0203 ------------------------------------------------------------------------------
0204 DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
0205 binding.
0206
0207 Required properties:
0208 - compatible : "ti,edma3"
0209 - #dma-cells: Should be set to <1>
0210 Clients should use a single channel number per DMA request.
0211 - reg: Memory map for accessing module
0212 - interrupts: Exactly 3 interrupts need to be specified in the order:
0213 1. Transfer completion interrupt.
0214 2. Memory protection interrupt.
0215 3. Error interrupt.
0216 Optional properties:
0217 - ti,hwmods: Name of the hwmods associated to the EDMA
0218 - ti,edma-xbar-event-map: Crossbar event to channel map
0219
0220 Deprecated properties:
0221 Listed here in case one wants to boot an old kernel with new DTB. These
0222 properties might need to be added to the new DTS files.
0223 - ti,edma-regions: Number of regions
0224 - ti,edma-slots: Number of slots
0225 - dma-channels: Specify total DMA channels per CC
0226
0227 Example:
0228
0229 edma: edma@49000000 {
0230 reg = <0x49000000 0x10000>;
0231 interrupt-parent = <&intc>;
0232 interrupts = <12 13 14>;
0233 compatible = "ti,edma3";
0234 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
0235 #dma-cells = <1>;
0236 ti,edma-xbar-event-map = /bits/ 16 <1 12
0237 2 13>;
0238 };
