0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ST-Ericsson DMA40 DMA Engine
0008
0009 maintainers:
0010 - Linus Walleij <linus.walleij@linaro.org>
0011
0012 allOf:
0013 - $ref: "dma-controller.yaml#"
0014
0015 properties:
0016 "#dma-cells":
0017 const: 3
0018 description: |
0019 The first cell is the unique device channel number as indicated by this
0020 table for DB8500 which is the only ASIC known to use DMA40:
0021
0022 0: SPI controller 0
0023 1: SD/MMC controller 0 (unused)
0024 2: SD/MMC controller 1 (unused)
0025 3: SD/MMC controller 2 (unused)
0026 4: I2C port 1
0027 5: I2C port 3
0028 6: I2C port 2
0029 7: I2C port 4
0030 8: Synchronous Serial Port SSP0
0031 9: Synchronous Serial Port SSP1
0032 10: Multi-Channel Display Engine MCDE RX
0033 11: UART port 2
0034 12: UART port 1
0035 13: UART port 0
0036 14: Multirate Serial Port MSP2
0037 15: I2C port 0
0038 16: USB OTG in/out endpoints 7 & 15
0039 17: USB OTG in/out endpoints 6 & 14
0040 18: USB OTG in/out endpoints 5 & 13
0041 19: USB OTG in/out endpoints 4 & 12
0042 20: SLIMbus or HSI channel 0
0043 21: SLIMbus or HSI channel 1
0044 22: SLIMbus or HSI channel 2
0045 23: SLIMbus or HSI channel 3
0046 24: Multimedia DSP SXA0
0047 25: Multimedia DSP SXA1
0048 26: Multimedia DSP SXA2
0049 27: Multimedia DSP SXA3
0050 28: SD/MMC controller 2
0051 29: SD/MMC controller 0
0052 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
0053 31: MSP port 0 or SLIMbus channel 0
0054 32: SD/MMC controller 1
0055 33: SPI controller 2
0056 34: i2c3 RX2 TX2
0057 35: SPI controller 1
0058 36: USB OTG in/out endpoints 3 & 11
0059 37: USB OTG in/out endpoints 2 & 10
0060 38: USB OTG in/out endpoints 1 & 9
0061 39: USB OTG in/out endpoints 8
0062 40: SPI controller 3
0063 41: SD/MMC controller 3
0064 42: SD/MMC controller 4
0065 43: SD/MMC controller 5
0066 44: Multimedia DSP SXA4
0067 45: Multimedia DSP SXA5
0068 46: SLIMbus channel 8 or Multimedia DSP SXA6
0069 47: SLIMbus channel 9 or Multimedia DSP SXA7
0070 48: Crypto Accelerator 1
0071 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
0072 50: Hash Accelerator 1 TX
0073 51: memcpy TX (to be used by the DMA driver for memcpy operations)
0074 52: SLIMbus or HSI channel 4
0075 53: SLIMbus or HSI channel 5
0076 54: SLIMbus or HSI channel 6
0077 55: SLIMbus or HSI channel 7
0078 56: memcpy (to be used by the DMA driver for memcpy operations)
0079 57: memcpy (to be used by the DMA driver for memcpy operations)
0080 58: memcpy (to be used by the DMA driver for memcpy operations)
0081 59: memcpy (to be used by the DMA driver for memcpy operations)
0082 60: memcpy (to be used by the DMA driver for memcpy operations)
0083 61: Crypto Accelerator 0
0084 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
0085 63: Hash Accelerator 0 TX
0086
0087 The second cell is the DMA request line number. This is only used when
0088 a fixed channel is allocated, and indicated by setting bit 3 in the
0089 flags field (see below).
0090
0091 The third cell is a 32bit flags bitfield with the following possible
0092 bits set:
0093 0x00000001 (bit 0) - mode:
0094 Logical channel when unset
0095 Physical channel when set
0096 0x00000002 (bit 1) - direction:
0097 Memory to Device when unset
0098 Device to Memory when set
0099 0x00000004 (bit 2) - endianness:
0100 Little endian when unset
0101 Big endian when set
0102 0x00000008 (bit 3) - use fixed channel:
0103 Use automatic channel selection when unset
0104 Use DMA request line number when set
0105 0x00000010 (bit 4) - set channel as high priority:
0106 Normal priority when unset
0107 High priority when set
0108
0109 compatible:
0110 items:
0111 - const: stericsson,db8500-dma40
0112 - const: stericsson,dma40
0113
0114 reg:
0115 items:
0116 - description: DMA40 memory base
0117 - description: LCPA memory base
0118
0119 reg-names:
0120 items:
0121 - const: base
0122 - const: lcpa
0123
0124 interrupts:
0125 maxItems: 1
0126
0127 clocks:
0128 maxItems: 1
0129
0130 memcpy-channels:
0131 $ref: /schemas/types.yaml#/definitions/uint32-array
0132 description: Array of u32 elements indicating which channels on the DMA
0133 engine are elegible for memcpy transfers
0134
0135 required:
0136 - "#dma-cells"
0137 - compatible
0138 - reg
0139 - interrupts
0140 - clocks
0141 - memcpy-channels
0142
0143 additionalProperties: false
0144
0145 examples:
0146 - |
0147 #include <dt-bindings/interrupt-controller/irq.h>
0148 #include <dt-bindings/interrupt-controller/arm-gic.h>
0149 #include <dt-bindings/mfd/dbx500-prcmu.h>
0150 dma-controller@801C0000 {
0151 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
0152 reg = <0x801C0000 0x1000>, <0x40010000 0x800>;
0153 reg-names = "base", "lcpa";
0154 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0155 #dma-cells = <3>;
0156 memcpy-channels = <56 57 58 59 60>;
0157 clocks = <&prcmu_clk PRCMU_DMACLK>;
0158 };
0159 ...
