0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: STMicroelectronics STM32 MDMA Controller bindings
0008
0009 description: |
0010 The STM32 MDMA is a general-purpose direct memory access controller capable of
0011 supporting 64 independent DMA channels with 256 HW requests.
0012 DMA clients connected to the STM32 MDMA controller must use the format
0013 described in the dma.txt file, using a five-cell specifier for each channel:
0014 a phandle to the MDMA controller plus the following five integer cells:
0015 1. The request line number
0016 2. The priority level
0017 0x0: Low
0018 0x1: Medium
0019 0x2: High
0020 0x3: Very high
0021 3. A 32bit mask specifying the DMA channel configuration
0022 -bit 0-1: Source increment mode
0023 0x0: Source address pointer is fixed
0024 0x2: Source address pointer is incremented after each data transfer
0025 0x3: Source address pointer is decremented after each data transfer
0026 -bit 2-3: Destination increment mode
0027 0x0: Destination address pointer is fixed
0028 0x2: Destination address pointer is incremented after each data transfer
0029 0x3: Destination address pointer is decremented after each data transfer
0030 -bit 8-9: Source increment offset size
0031 0x0: byte (8bit)
0032 0x1: half-word (16bit)
0033 0x2: word (32bit)
0034 0x3: double-word (64bit)
0035 -bit 10-11: Destination increment offset size
0036 0x0: byte (8bit)
0037 0x1: half-word (16bit)
0038 0x2: word (32bit)
0039 0x3: double-word (64bit)
0040 -bit 25-18: The number of bytes to be transferred in a single transfer
0041 (min = 1 byte, max = 128 bytes)
0042 -bit 29:28: Trigger Mode
0043 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
0044 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
0045 0x2: Each MDMA request triggers a repeated block transfer
0046 0x3: Each MDMA request triggers a linked list transfer
0047 4. A 32bit value specifying the register to be used to acknowledge the request
0048 if no HW ack signal is used by the MDMA client
0049 5. A 32bit mask specifying the value to be written to acknowledge the request
0050 if no HW ack signal is used by the MDMA client
0051
0052 maintainers:
0053 - Amelie Delaunay <amelie.delaunay@foss.st.com>
0054
0055 allOf:
0056 - $ref: "dma-controller.yaml#"
0057
0058 properties:
0059 "#dma-cells":
0060 const: 5
0061
0062 compatible:
0063 const: st,stm32h7-mdma
0064
0065 reg:
0066 maxItems: 1
0067
0068 clocks:
0069 maxItems: 1
0070
0071 interrupts:
0072 maxItems: 1
0073
0074 resets:
0075 maxItems: 1
0076
0077 st,ahb-addr-masks:
0078 $ref: /schemas/types.yaml#/definitions/uint32-array
0079 description: Array of u32 mask to list memory devices addressed via AHB bus.
0080
0081 required:
0082 - compatible
0083 - reg
0084 - clocks
0085 - interrupts
0086
0087 unevaluatedProperties: false
0088
0089 examples:
0090 - |
0091 #include <dt-bindings/interrupt-controller/arm-gic.h>
0092 #include <dt-bindings/clock/stm32mp1-clks.h>
0093 #include <dt-bindings/reset/stm32mp1-resets.h>
0094 dma-controller@52000000 {
0095 compatible = "st,stm32h7-mdma";
0096 reg = <0x52000000 0x1000>;
0097 interrupts = <122>;
0098 clocks = <&timer_clk>;
0099 resets = <&rcc 992>;
0100 #dma-cells = <5>;
0101 dma-channels = <16>;
0102 dma-requests = <32>;
0103 st,ahb-addr-masks = <0x20000000>, <0x00000000>;
0104 };
0105
0106 ...
