0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: STMicroelectronics STM32 DMA Controller bindings
0008
0009 description: |
0010 The STM32 DMA is a general-purpose direct memory access controller capable of
0011 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
0012 DMA clients connected to the STM32 DMA controller must use the format
0013 described in the dma.txt file, using a four-cell specifier for each
0014 channel: a phandle to the DMA controller plus the following four integer cells:
0015 1. The channel id
0016 2. The request line number
0017 3. A 32bit mask specifying the DMA channel configuration which are device
0018 dependent:
0019 -bit 9: Peripheral Increment Address
0020 0x0: no address increment between transfers
0021 0x1: increment address between transfers
0022 -bit 10: Memory Increment Address
0023 0x0: no address increment between transfers
0024 0x1: increment address between transfers
0025 -bit 15: Peripheral Increment Offset Size
0026 0x0: offset size is linked to the peripheral bus width
0027 0x1: offset size is fixed to 4 (32-bit alignment)
0028 -bit 16-17: Priority level
0029 0x0: low
0030 0x1: medium
0031 0x2: high
0032 0x3: very high
0033 4. A 32bit bitfield value specifying DMA features which are device dependent:
0034 -bit 0-1: DMA FIFO threshold selection
0035 0x0: 1/4 full FIFO
0036 0x1: 1/2 full FIFO
0037 0x2: 3/4 full FIFO
0038 0x3: full FIFO
0039 -bit 2: DMA direct mode
0040 0x0: FIFO mode with threshold selectable with bit 0-1
0041 0x1: Direct mode: each DMA request immediately initiates a transfer
0042 from/to the memory, FIFO is bypassed.
0043 -bit 4: alternative DMA request/acknowledge protocol
0044 0x0: Use standard DMA ACK management, where ACK signal is maintained
0045 up to the removal of request and transfer completion
0046 0x1: Use alternative DMA ACK management, where ACK de-assertion does
0047 not wait for the de-assertion of the REQuest, ACK is only managed
0048 by transfer completion. This must only be used on channels
0049 managing transfers for STM32 USART/UART.
0050
0051
0052 maintainers:
0053 - Amelie Delaunay <amelie.delaunay@foss.st.com>
0054
0055 allOf:
0056 - $ref: "dma-controller.yaml#"
0057
0058 properties:
0059 "#dma-cells":
0060 const: 4
0061
0062 compatible:
0063 const: st,stm32-dma
0064
0065 reg:
0066 maxItems: 1
0067
0068 clocks:
0069 maxItems: 1
0070
0071 interrupts:
0072 maxItems: 8
0073 description: Should contain all of the per-channel DMA
0074 interrupts in ascending order with respect to the
0075 DMA channel index.
0076
0077 resets:
0078 maxItems: 1
0079
0080 st,mem2mem:
0081 $ref: /schemas/types.yaml#/definitions/flag
0082 description: if defined, it indicates that the controller
0083 supports memory-to-memory transfer
0084
0085 required:
0086 - compatible
0087 - reg
0088 - clocks
0089 - interrupts
0090
0091 unevaluatedProperties: false
0092
0093 examples:
0094 - |
0095 #include <dt-bindings/interrupt-controller/arm-gic.h>
0096 #include <dt-bindings/clock/stm32mp1-clks.h>
0097 #include <dt-bindings/reset/stm32mp1-resets.h>
0098 dma-controller@40026400 {
0099 compatible = "st,stm32-dma";
0100 reg = <0x40026400 0x400>;
0101 interrupts = <56>,
0102 <57>,
0103 <58>,
0104 <59>,
0105 <60>,
0106 <68>,
0107 <69>,
0108 <70>;
0109 clocks = <&clk_hclk>;
0110 #dma-cells = <4>;
0111 st,mem2mem;
0112 resets = <&rcc 150>;
0113 dma-requests = <8>;
0114 };
0115
0116 ...
