0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Synopsys Designware DMA Controller
0008
0009 maintainers:
0010 - Viresh Kumar <vireshk@kernel.org>
0011 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0012
0013 allOf:
0014 - $ref: "dma-controller.yaml#"
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - const: snps,dma-spear1340
0020 - items:
0021 - enum:
0022 - renesas,r9a06g032-dma
0023 - const: renesas,rzn1-dma
0024
0025
0026 "#dma-cells":
0027 minimum: 3
0028 maximum: 4
0029 description: |
0030 First cell is a phandle pointing to the DMA controller. Second one is
0031 the DMA request line number. Third cell is the memory master identifier
0032 for transfers on dynamically allocated channel. Fourth cell is the
0033 peripheral master identifier for transfers on an allocated channel. Fifth
0034 cell is an optional mask of the DMA channels permitted to be allocated
0035 for the corresponding client device.
0036
0037 reg:
0038 maxItems: 1
0039
0040 interrupts:
0041 maxItems: 1
0042
0043 clocks:
0044 maxItems: 1
0045
0046 clock-names:
0047 description: AHB interface reference clock.
0048 const: hclk
0049
0050 dma-channels:
0051 description: |
0052 Number of DMA channels supported by the controller. In case if
0053 not specified the driver will try to auto-detect this and
0054 the rest of the optional parameters.
0055 minimum: 1
0056 maximum: 8
0057
0058 dma-requests:
0059 minimum: 1
0060 maximum: 16
0061
0062 dma-masters:
0063 $ref: /schemas/types.yaml#/definitions/uint32
0064 description: |
0065 Number of DMA masters supported by the controller. In case if
0066 not specified the driver will try to auto-detect this and
0067 the rest of the optional parameters.
0068 minimum: 1
0069 maximum: 4
0070
0071 chan_allocation_order:
0072 $ref: /schemas/types.yaml#/definitions/uint32
0073 description: |
0074 DMA channels allocation order specifier. Zero means ascending order
0075 (first free allocated), while one - descending (last free allocated).
0076 default: 0
0077 enum: [0, 1]
0078
0079 chan_priority:
0080 $ref: /schemas/types.yaml#/definitions/uint32
0081 description: |
0082 DMA channels priority order. Zero means ascending channels priority
0083 so the very first channel has the highest priority. While 1 means
0084 descending priority (the last channel has the highest priority).
0085 default: 0
0086 enum: [0, 1]
0087
0088 block_size:
0089 $ref: /schemas/types.yaml#/definitions/uint32
0090 description: Maximum block size supported by the DMA controller.
0091 enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
0092
0093 data-width:
0094 $ref: /schemas/types.yaml#/definitions/uint32-array
0095 description: Data bus width per each DMA master in bytes.
0096 items:
0097 maxItems: 4
0098 items:
0099 enum: [4, 8, 16, 32]
0100
0101 data_width:
0102 $ref: /schemas/types.yaml#/definitions/uint32-array
0103 deprecated: true
0104 description: |
0105 Data bus width per each DMA master in (2^n * 8) bits. This property is
0106 deprecated. It' usage is discouraged in favor of data-width one. Moreover
0107 the property incorrectly permits to define data-bus width of 8 and 16
0108 bits, which is impossible in accordance with DW DMAC IP-core data book.
0109 items:
0110 maxItems: 4
0111 items:
0112 enum:
0113 - 0 # 8 bits
0114 - 1 # 16 bits
0115 - 2 # 32 bits
0116 - 3 # 64 bits
0117 - 4 # 128 bits
0118 - 5 # 256 bits
0119 default: 0
0120
0121 multi-block:
0122 $ref: /schemas/types.yaml#/definitions/uint32-array
0123 description: |
0124 LLP-based multi-block transfer supported by hardware per
0125 each DMA channel.
0126 items:
0127 maxItems: 8
0128 items:
0129 enum: [0, 1]
0130 default: 1
0131
0132 snps,max-burst-len:
0133 $ref: /schemas/types.yaml#/definitions/uint32-array
0134 description: |
0135 Maximum length of the burst transactions supported by the controller.
0136 This property defines the upper limit of the run-time burst setting
0137 (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
0138 will be from 1 to max-burst-len words. It's an array property with one
0139 cell per channel in the units determined by the value set in the
0140 CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
0141 items:
0142 maxItems: 8
0143 items:
0144 enum: [4, 8, 16, 32, 64, 128, 256]
0145 default: 256
0146
0147 snps,dma-protection-control:
0148 $ref: /schemas/types.yaml#/definitions/uint32
0149 description: |
0150 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
0151 indicates the following features: bit 0 - privileged mode,
0152 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
0153 default: 0
0154 minimum: 0
0155 maximum: 7
0156
0157 unevaluatedProperties: false
0158
0159 required:
0160 - compatible
0161 - "#dma-cells"
0162 - reg
0163 - interrupts
0164
0165 examples:
0166 - |
0167 dma-controller@fc000000 {
0168 compatible = "snps,dma-spear1340";
0169 reg = <0xfc000000 0x1000>;
0170 interrupt-parent = <&vic1>;
0171 interrupts = <12>;
0172
0173 dma-channels = <8>;
0174 dma-requests = <16>;
0175 dma-masters = <4>;
0176 #dma-cells = <3>;
0177
0178 chan_allocation_order = <1>;
0179 chan_priority = <1>;
0180 block_size = <0xfff>;
0181 data-width = <8 8>;
0182 multi-block = <0 0 0 0 0 0 0 0>;
0183 snps,max-burst-len = <16 16 4 4 4 4 4 4>;
0184 };
0185 ...
