0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: SiFive Unleashed Rev C000 Platform DMA
0008
0009 maintainers:
0010 - Green Wan <green.wan@sifive.com>
0011 - Palmer Debbelt <palmer@sifive.com>
0012 - Paul Walmsley <paul.walmsley@sifive.com>
0013
0014 description: |
0015 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
0016 channels. Each channel has 2 interrupts. One is for DMA done and
0017 the other is for DME error.
0018
0019 In different SoC, DMA could be attached to different IRQ line.
0020 DT file need to be changed to meet the difference. For technical
0021 doc,
0022
0023 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
0024
0025 allOf:
0026 - $ref: "dma-controller.yaml#"
0027
0028 properties:
0029 compatible:
0030 items:
0031 - enum:
0032 - sifive,fu540-c000-pdma
0033 - const: sifive,pdma0
0034 description:
0035 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
0036 Supported compatible strings are -
0037 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
0038 SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
0039 with no chip integration tweaks.
0040
0041 reg:
0042 maxItems: 1
0043
0044 interrupts:
0045 minItems: 1
0046 maxItems: 8
0047
0048 dma-channels:
0049 description: For backwards-compatibility, the default value is 4
0050 minimum: 1
0051 maximum: 4
0052 default: 4
0053
0054 '#dma-cells':
0055 const: 1
0056
0057 required:
0058 - compatible
0059 - reg
0060 - interrupts
0061
0062 unevaluatedProperties: false
0063
0064 examples:
0065 - |
0066 dma-controller@3000000 {
0067 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
0068 reg = <0x3000000 0x8000>;
0069 dma-channels = <4>;
0070 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
0071 #dma-cells = <1>;
0072 };
0073
0074 ...
