0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
0008
0009 maintainers:
0010 - Biju Das <biju.das.jz@bp.renesas.com>
0011
0012 allOf:
0013 - $ref: "dma-controller.yaml#"
0014
0015 properties:
0016 compatible:
0017 items:
0018 - enum:
0019 - renesas,r9a07g043-dmac # RZ/G2UL
0020 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
0021 - renesas,r9a07g054-dmac # RZ/V2L
0022 - const: renesas,rz-dmac
0023
0024 reg:
0025 items:
0026 - description: Control and channel register block
0027 - description: DMA extended resource selector block
0028
0029 interrupts:
0030 maxItems: 17
0031
0032 interrupt-names:
0033 items:
0034 - const: error
0035 - const: ch0
0036 - const: ch1
0037 - const: ch2
0038 - const: ch3
0039 - const: ch4
0040 - const: ch5
0041 - const: ch6
0042 - const: ch7
0043 - const: ch8
0044 - const: ch9
0045 - const: ch10
0046 - const: ch11
0047 - const: ch12
0048 - const: ch13
0049 - const: ch14
0050 - const: ch15
0051
0052 clocks:
0053 items:
0054 - description: DMA main clock
0055 - description: DMA register access clock
0056
0057 '#dma-cells':
0058 const: 1
0059 description:
0060 The cell specifies the encoded MID/RID values of the DMAC port
0061 connected to the DMA client and the slave channel configuration
0062 parameters.
0063 bits[0:9] - Specifies MID/RID value
0064 bit[10] - Specifies DMA request high enable (HIEN)
0065 bit[11] - Specifies DMA request detection type (LVL)
0066 bits[12:14] - Specifies DMAACK output mode (AM)
0067 bit[15] - Specifies Transfer Mode (TM)
0068
0069 dma-channels:
0070 const: 16
0071
0072 power-domains:
0073 maxItems: 1
0074
0075 resets:
0076 items:
0077 - description: Reset for DMA ARESETN reset terminal
0078 - description: Reset for DMA RST_ASYNC reset terminal
0079
0080 required:
0081 - compatible
0082 - reg
0083 - interrupts
0084 - interrupt-names
0085 - clocks
0086 - '#dma-cells'
0087 - dma-channels
0088 - power-domains
0089 - resets
0090
0091 additionalProperties: false
0092
0093 examples:
0094 - |
0095 #include <dt-bindings/interrupt-controller/arm-gic.h>
0096 #include <dt-bindings/clock/r9a07g044-cpg.h>
0097
0098 dmac: dma-controller@11820000 {
0099 compatible = "renesas,r9a07g044-dmac",
0100 "renesas,rz-dmac";
0101 reg = <0x11820000 0x10000>,
0102 <0x11830000 0x10000>;
0103 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
0104 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
0105 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
0106 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
0107 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
0108 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
0109 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
0110 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
0111 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
0112 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
0113 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
0114 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
0115 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
0116 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
0117 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
0118 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
0119 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
0120 interrupt-names = "error",
0121 "ch0", "ch1", "ch2", "ch3",
0122 "ch4", "ch5", "ch6", "ch7",
0123 "ch8", "ch9", "ch10", "ch11",
0124 "ch12", "ch13", "ch14", "ch15";
0125 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
0126 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
0127 power-domains = <&cpg>;
0128 resets = <&cpg R9A07G044_DMAC_ARESETN>,
0129 <&cpg R9A07G044_DMAC_RST_ASYNC>;
0130 #dma-cells = <1>;
0131 dma-channels = <16>;
0132 };
