0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Renesas R-Car and RZ/G DMA Controller
0008
0009 maintainers:
0010 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
0011
0012 allOf:
0013 - $ref: "dma-controller.yaml#"
0014
0015 properties:
0016 compatible:
0017 oneOf:
0018 - items:
0019 - enum:
0020 - renesas,dmac-r8a7742 # RZ/G1H
0021 - renesas,dmac-r8a7743 # RZ/G1M
0022 - renesas,dmac-r8a7744 # RZ/G1N
0023 - renesas,dmac-r8a7745 # RZ/G1E
0024 - renesas,dmac-r8a77470 # RZ/G1C
0025 - renesas,dmac-r8a774a1 # RZ/G2M
0026 - renesas,dmac-r8a774b1 # RZ/G2N
0027 - renesas,dmac-r8a774c0 # RZ/G2E
0028 - renesas,dmac-r8a774e1 # RZ/G2H
0029 - renesas,dmac-r8a7790 # R-Car H2
0030 - renesas,dmac-r8a7791 # R-Car M2-W
0031 - renesas,dmac-r8a7792 # R-Car V2H
0032 - renesas,dmac-r8a7793 # R-Car M2-N
0033 - renesas,dmac-r8a7794 # R-Car E2
0034 - renesas,dmac-r8a7795 # R-Car H3
0035 - renesas,dmac-r8a7796 # R-Car M3-W
0036 - renesas,dmac-r8a77961 # R-Car M3-W+
0037 - renesas,dmac-r8a77965 # R-Car M3-N
0038 - renesas,dmac-r8a77970 # R-Car V3M
0039 - renesas,dmac-r8a77980 # R-Car V3H
0040 - renesas,dmac-r8a77990 # R-Car E3
0041 - renesas,dmac-r8a77995 # R-Car D3
0042 - const: renesas,rcar-dmac
0043
0044 - items:
0045 - enum:
0046 - renesas,dmac-r8a779a0 # R-Car V3U
0047 - renesas,dmac-r8a779f0 # R-Car S4-8
0048 - const: renesas,rcar-gen4-dmac # R-Car Gen4
0049
0050 reg: true
0051
0052 interrupts:
0053 minItems: 9
0054 maxItems: 17
0055
0056 interrupt-names:
0057 minItems: 9
0058 items:
0059 - const: error
0060 - pattern: "^ch([0-9]|1[0-5])$"
0061 - pattern: "^ch([0-9]|1[0-5])$"
0062 - pattern: "^ch([0-9]|1[0-5])$"
0063 - pattern: "^ch([0-9]|1[0-5])$"
0064 - pattern: "^ch([0-9]|1[0-5])$"
0065 - pattern: "^ch([0-9]|1[0-5])$"
0066 - pattern: "^ch([0-9]|1[0-5])$"
0067 - pattern: "^ch([0-9]|1[0-5])$"
0068 - pattern: "^ch([0-9]|1[0-5])$"
0069 - pattern: "^ch([0-9]|1[0-5])$"
0070 - pattern: "^ch([0-9]|1[0-5])$"
0071 - pattern: "^ch([0-9]|1[0-5])$"
0072 - pattern: "^ch([0-9]|1[0-5])$"
0073 - pattern: "^ch([0-9]|1[0-5])$"
0074 - pattern: "^ch([0-9]|1[0-5])$"
0075 - pattern: "^ch([0-9]|1[0-5])$"
0076
0077 clocks:
0078 maxItems: 1
0079
0080 clock-names:
0081 items:
0082 - const: fck
0083
0084 '#dma-cells':
0085 const: 1
0086 description:
0087 The cell specifies the MID/RID of the DMAC port connected to
0088 the DMA client.
0089
0090 dma-channels:
0091 minimum: 8
0092 maximum: 16
0093
0094 dma-channel-mask: true
0095
0096 iommus:
0097 minItems: 8
0098 maxItems: 16
0099
0100 power-domains:
0101 maxItems: 1
0102
0103 resets:
0104 maxItems: 1
0105
0106 required:
0107 - compatible
0108 - reg
0109 - interrupts
0110 - interrupt-names
0111 - clocks
0112 - clock-names
0113 - '#dma-cells'
0114 - dma-channels
0115 - power-domains
0116 - resets
0117
0118 if:
0119 properties:
0120 compatible:
0121 contains:
0122 enum:
0123 - renesas,rcar-gen4-dmac
0124 then:
0125 properties:
0126 reg:
0127 items:
0128 - description: Base register block
0129 - description: Channel register block
0130 else:
0131 properties:
0132 reg:
0133 maxItems: 1
0134
0135 additionalProperties: false
0136
0137 examples:
0138 - |
0139 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
0140 #include <dt-bindings/interrupt-controller/arm-gic.h>
0141 #include <dt-bindings/power/r8a7790-sysc.h>
0142
0143 dmac0: dma-controller@e6700000 {
0144 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
0145 reg = <0xe6700000 0x20000>;
0146 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0160 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
0162 interrupt-names = "error",
0163 "ch0", "ch1", "ch2", "ch3",
0164 "ch4", "ch5", "ch6", "ch7",
0165 "ch8", "ch9", "ch10", "ch11",
0166 "ch12", "ch13", "ch14";
0167 clocks = <&cpg CPG_MOD 219>;
0168 clock-names = "fck";
0169 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
0170 resets = <&cpg 219>;
0171 #dma-cells = <1>;
0172 dma-channels = <15>;
0173 };
