0001 QCOM ADM DMA Controller
0002
0003 Required properties:
0004 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
0005 - reg: Address range for DMA registers
0006 - interrupts: Should contain one interrupt shared by all channels
0007 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
0008 denotes CRCI (client rate control interface) flow control assignment.
0009 - clocks: Should contain the core clock and interface clock.
0010 - clock-names: Must contain "core" for the core clock and "iface" for the
0011 interface clock.
0012 - resets: Must contain an entry for each entry in reset names.
0013 - reset-names: Must include the following entries:
0014 - clk
0015 - c0
0016 - c1
0017 - c2
0018 - qcom,ee: indicates the security domain identifier used in the secure world.
0019
0020 Example:
0021 adm_dma: dma@18300000 {
0022 compatible = "qcom,adm";
0023 reg = <0x18300000 0x100000>;
0024 interrupts = <0 170 0>;
0025 #dma-cells = <2>;
0026
0027 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
0028 clock-names = "core", "iface";
0029
0030 resets = <&gcc ADM0_RESET>,
0031 <&gcc ADM0_C0_RESET>,
0032 <&gcc ADM0_C1_RESET>,
0033 <&gcc ADM0_C2_RESET>;
0034 reset-names = "clk", "c0", "c1", "c2";
0035 qcom,ee = <0>;
0036 };
0037
0038 DMA clients must use the format descripted in the dma.txt file, using a three
0039 cell specifier for each channel.
0040
0041 Each dmas request consists of 3 cells:
0042 1. phandle pointing to the DMA controller
0043 2. channel number
0044 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
0045 The CRCI is used for flow control. It identifies the peripheral device that
0046 is the source/destination for the transferred data.
0047
0048 Example:
0049
0050 spi4: spi@1a280000 {
0051 spi-max-frequency = <50000000>;
0052
0053 pinctrl-0 = <&spi_pins>;
0054 pinctrl-names = "default";
0055
0056 cs-gpios = <&qcom_pinmux 20 0>;
0057
0058 dmas = <&adm_dma 6 9>,
0059 <&adm_dma 5 10>;
0060 dma-names = "rx", "tx";
0061 };
