0001 * NVIDIA Tegra APB DMA controller
0002
0003 Required properties:
0004 - compatible: Should be "nvidia,<chip>-apbdma"
0005 - reg: Should contain DMA registers location and length. This shuld include
0006 all of the per-channel registers.
0007 - interrupts: Should contain all of the per-channel DMA interrupts.
0008 - clocks: Must contain one entry, for the module clock.
0009 See ../clocks/clock-bindings.txt for details.
0010 - resets : Must contain an entry for each entry in reset-names.
0011 See ../reset/reset.txt for details.
0012 - reset-names : Must include the following entries:
0013 - dma
0014 - #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
0015 client nodes' dmas properties. The specifier represents the DMA request
0016 select value for the peripheral. For more details, consult the Tegra TRM's
0017 documentation of the APB DMA channel control register REQ_SEL field.
0018
0019 Examples:
0020
0021 apbdma: dma@6000a000 {
0022 compatible = "nvidia,tegra20-apbdma";
0023 reg = <0x6000a000 0x1200>;
0024 interrupts = < 0 136 0x04
0025 0 137 0x04
0026 0 138 0x04
0027 0 139 0x04
0028 0 140 0x04
0029 0 141 0x04
0030 0 142 0x04
0031 0 143 0x04
0032 0 144 0x04
0033 0 145 0x04
0034 0 146 0x04
0035 0 147 0x04
0036 0 148 0x04
0037 0 149 0x04
0038 0 150 0x04
0039 0 151 0x04 >;
0040 clocks = <&tegra_car 34>;
0041 resets = <&tegra_car 34>;
0042 reset-names = "dma";
0043 #dma-cells = <1>;
0044 };
