0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
0008
0009 description: |
0010 The Tegra General Purpose Central (GPC) DMA controller is used for faster
0011 data transfers between memory to memory, memory to device and device to
0012 memory.
0013
0014 maintainers:
0015 - Jon Hunter <jonathanh@nvidia.com>
0016 - Rajesh Gumasta <rgumasta@nvidia.com>
0017
0018 allOf:
0019 - $ref: "dma-controller.yaml#"
0020
0021 properties:
0022 compatible:
0023 oneOf:
0024 - const: nvidia,tegra186-gpcdma
0025 - items:
0026 - enum:
0027 - nvidia,tegra234-gpcdma
0028 - nvidia,tegra194-gpcdma
0029 - const: nvidia,tegra186-gpcdma
0030
0031 "#dma-cells":
0032 const: 1
0033
0034 reg:
0035 maxItems: 1
0036
0037 interrupts:
0038 description:
0039 Should contain all of the per-channel DMA interrupts in
0040 ascending order with respect to the DMA channel index.
0041 minItems: 1
0042 maxItems: 31
0043
0044 resets:
0045 maxItems: 1
0046
0047 reset-names:
0048 const: gpcdma
0049
0050 iommus:
0051 maxItems: 1
0052
0053 dma-coherent: true
0054
0055 required:
0056 - compatible
0057 - reg
0058 - interrupts
0059 - resets
0060 - reset-names
0061 - "#dma-cells"
0062 - iommus
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068 #include <dt-bindings/interrupt-controller/arm-gic.h>
0069 #include <dt-bindings/memory/tegra186-mc.h>
0070 #include <dt-bindings/reset/tegra186-reset.h>
0071
0072 dma-controller@2600000 {
0073 compatible = "nvidia,tegra186-gpcdma";
0074 reg = <0x2600000 0x210000>;
0075 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
0076 reset-names = "gpcdma";
0077 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0078 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0079 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
0081 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
0082 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
0083 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0085 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0086 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0087 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
0088 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0090 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0098 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0099 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0100 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0101 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0108 #dma-cells = <1>;
0109 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
0110 dma-coherent;
0111 };
0112 ...
