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OSCL-LXR

 
 

    


0001 MediaTek High-Speed DMA Controller
0002 ==================================
0003 
0004 This device follows the generic DMA bindings defined in dma/dma.txt.
0005 
0006 Required properties:
0007 
0008 - compatible:   Must be one of
0009                   "mediatek,mt7622-hsdma": for MT7622 SoC
0010                   "mediatek,mt7623-hsdma": for MT7623 SoC
0011 - reg:          Should contain the register's base address and length.
0012 - interrupts:   Should contain a reference to the interrupt used by this
0013                 device.
0014 - clocks:       Should be the clock specifiers corresponding to the entry in
0015                 clock-names property.
0016 - clock-names:  Should contain "hsdma" entries.
0017 - power-domains: Phandle to the power domain that the device is part of
0018 - #dma-cells:   The length of the DMA specifier, must be <1>. This one cell
0019                 in dmas property of a client device represents the channel
0020                 number.
0021 Example:
0022 
0023         hsdma: dma-controller@1b007000 {
0024                 compatible = "mediatek,mt7623-hsdma";
0025                 reg = <0 0x1b007000 0 0x1000>;
0026                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
0027                 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
0028                 clock-names = "hsdma";
0029                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
0030                 #dma-cells = <1>;
0031         };
0032 
0033 DMA clients must use the format described in dma/dma.txt file.