0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek UART APDMA controller
0008
0009 maintainers:
0010 - Long Cheng <long.cheng@mediatek.com>
0011
0012 description: |
0013 The MediaTek UART APDMA controller provides DMA capabilities
0014 for the UART peripheral bus.
0015
0016 allOf:
0017 - $ref: "dma-controller.yaml#"
0018
0019 properties:
0020 compatible:
0021 oneOf:
0022 - items:
0023 - enum:
0024 - mediatek,mt2712-uart-dma
0025 - mediatek,mt8365-uart-dma
0026 - mediatek,mt8516-uart-dma
0027 - const: mediatek,mt6577-uart-dma
0028 - enum:
0029 - mediatek,mt6577-uart-dma
0030
0031 reg:
0032 minItems: 1
0033 maxItems: 16
0034
0035 interrupts:
0036 description: |
0037 TX, RX interrupt lines for each UART APDMA channel
0038 minItems: 1
0039 maxItems: 16
0040
0041 clocks:
0042 description: Must contain one entry for the APDMA main clock
0043 maxItems: 1
0044
0045 clock-names:
0046 const: apdma
0047
0048 "#dma-cells":
0049 const: 1
0050 description: |
0051 The first cell specifies the UART APDMA channel number
0052
0053 dma-requests:
0054 description: |
0055 Number of virtual channels of the UART APDMA controller
0056 maximum: 16
0057
0058 mediatek,dma-33bits:
0059 type: boolean
0060 description: Enable 33-bits UART APDMA support
0061
0062 required:
0063 - compatible
0064 - reg
0065 - interrupts
0066
0067 additionalProperties: false
0068
0069 if:
0070 not:
0071 required:
0072 - dma-requests
0073 then:
0074 properties:
0075 interrupts:
0076 maxItems: 8
0077 reg:
0078 maxItems: 8
0079
0080 examples:
0081 - |
0082 #include <dt-bindings/interrupt-controller/arm-gic.h>
0083 #include <dt-bindings/clock/mt2712-clk.h>
0084 soc {
0085 #address-cells = <2>;
0086 #size-cells = <2>;
0087
0088 apdma: dma-controller@11000400 {
0089 compatible = "mediatek,mt2712-uart-dma",
0090 "mediatek,mt6577-uart-dma";
0091 reg = <0 0x11000400 0 0x80>,
0092 <0 0x11000480 0 0x80>,
0093 <0 0x11000500 0 0x80>,
0094 <0 0x11000580 0 0x80>,
0095 <0 0x11000600 0 0x80>,
0096 <0 0x11000680 0 0x80>,
0097 <0 0x11000700 0 0x80>,
0098 <0 0x11000780 0 0x80>,
0099 <0 0x11000800 0 0x80>,
0100 <0 0x11000880 0 0x80>,
0101 <0 0x11000900 0 0x80>,
0102 <0 0x11000980 0 0x80>;
0103 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
0104 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
0105 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
0106 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
0107 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
0108 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
0109 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
0110 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
0111 <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
0112 <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
0113 <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
0114 <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
0115 dma-requests = <12>;
0116 clocks = <&pericfg CLK_PERI_AP_DMA>;
0117 clock-names = "apdma";
0118 mediatek,dma-33bits;
0119 #dma-cells = <1>;
0120 };
0121 };
0122
0123 ...
