0001 NXP LPC18xx/43xx DMA MUX (DMA request router)
0002
0003 Required properties:
0004 - compatible: "nxp,lpc1850-dmamux"
0005 - reg: Memory map for accessing module
0006 - #dma-cells: Should be set to <3>.
0007 * 1st cell contain the master dma request signal
0008 * 2nd cell contain the mux value (0-3) for the peripheral
0009 * 3rd cell contain either 1 or 2 depending on the AHB
0010 master used.
0011 - dma-requests: Number of DMA requests for the mux
0012 - dma-masters: phandle pointing to the DMA controller
0013
0014 The DMA controller node need to have the following poroperties:
0015 - dma-requests: Number of DMA requests the controller can handle
0016
0017 Example:
0018
0019 dmac: dma@40002000 {
0020 compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
0021 arm,primecell-periphid = <0x00041080>;
0022 reg = <0x40002000 0x1000>;
0023 interrupts = <2>;
0024 clocks = <&ccu1 CLK_CPU_DMA>;
0025 clock-names = "apb_pclk";
0026 #dma-cells = <2>;
0027 dma-channels = <8>;
0028 dma-requests = <16>;
0029 lli-bus-interface-ahb1;
0030 lli-bus-interface-ahb2;
0031 mem-bus-interface-ahb1;
0032 mem-bus-interface-ahb2;
0033 memcpy-burst-size = <256>;
0034 memcpy-bus-width = <32>;
0035 };
0036
0037 dmamux: dma-mux {
0038 compatible = "nxp,lpc1850-dmamux";
0039 #dma-cells = <3>;
0040 dma-requests = <64>;
0041 dma-masters = <&dmac>;
0042 };
0043
0044 uart0: serial@40081000 {
0045 compatible = "nxp,lpc1850-uart", "ns16550a";
0046 reg = <0x40081000 0x1000>;
0047 reg-shift = <2>;
0048 interrupts = <24>;
0049 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
0050 clock-names = "uartclk", "reg";
0051 dmas = <&dmamux 1 1 2
0052 &dmamux 2 1 2>;
0053 dma-names = "tx", "rx";
0054 };
