0001 * Hisilicon K3 DMA controller
0002
0003 See dma.txt first
0004
0005 Required properties:
0006 - compatible: Must be one of
0007 - "hisilicon,k3-dma-1.0"
0008 - "hisilicon,hisi-pcm-asp-dma-1.0"
0009 - reg: Should contain DMA registers location and length.
0010 - interrupts: Should contain one interrupt shared by all channel
0011 - #dma-cells: see dma.txt, should be 1, para number
0012 - dma-channels: physical channels supported
0013 - dma-requests: virtual channels supported, each virtual channel
0014 have specific request line
0015 - clocks: clock required
0016
0017 Example:
0018
0019 Controller:
0020 dma0: dma@fcd02000 {
0021 compatible = "hisilicon,k3-dma-1.0";
0022 reg = <0xfcd02000 0x1000>;
0023 #dma-cells = <1>;
0024 dma-channels = <16>;
0025 dma-requests = <27>;
0026 interrupts = <0 12 4>;
0027 clocks = <&pclk>;
0028 };
0029
0030 Client:
0031 Use specific request line passing from dmax
0032 For example, i2c0 read channel request line is 18, while write channel use 19
0033
0034 i2c0: i2c@fcb08000 {
0035 compatible = "snps,designware-i2c";
0036 dmas = <&dma0 18 /* read channel */
0037 &dma0 19>; /* write channel */
0038 dma-names = "rx", "tx";
0039 };
0040
0041 i2c1: i2c@fcb09000 {
0042 compatible = "snps,designware-i2c";
0043 dmas = <&dma0 20 /* read channel */
0044 &dma0 21>; /* write channel */
0045 dma-names = "rx", "tx";
0046 };
0047
