0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Lightning Mountain centralized DMA controllers.
0008
0009 maintainers:
0010 - chuanhua.lei@intel.com
0011 - mallikarjunax.reddy@intel.com
0012
0013 allOf:
0014 - $ref: "dma-controller.yaml#"
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - intel,lgm-cdma
0020 - intel,lgm-dma2tx
0021 - intel,lgm-dma1rx
0022 - intel,lgm-dma1tx
0023 - intel,lgm-dma0tx
0024 - intel,lgm-dma3
0025 - intel,lgm-toe-dma30
0026 - intel,lgm-toe-dma31
0027
0028 reg:
0029 maxItems: 1
0030
0031 "#dma-cells":
0032 const: 3
0033 description:
0034 The first cell is the peripheral's DMA request line.
0035 The second cell is the peripheral's (port) number corresponding to the channel.
0036 The third cell is the burst length of the channel.
0037
0038 dma-channels:
0039 minimum: 1
0040 maximum: 16
0041
0042 dma-channel-mask:
0043 maxItems: 1
0044
0045 clocks:
0046 maxItems: 1
0047
0048 resets:
0049 maxItems: 1
0050
0051 reset-names:
0052 items:
0053 - const: ctrl
0054
0055 interrupts:
0056 maxItems: 1
0057
0058 intel,dma-poll-cnt:
0059 $ref: /schemas/types.yaml#/definitions/uint32
0060 description:
0061 DMA descriptor polling counter is used to control the poling mechanism
0062 for the descriptor fetching for all channels.
0063
0064 intel,dma-byte-en:
0065 type: boolean
0066 description:
0067 DMA byte enable is only valid for DMA write(RX).
0068 Byte enable(1) means DMA write will be based on the number of dwords
0069 instead of the whole burst.
0070
0071 intel,dma-drb:
0072 type: boolean
0073 description:
0074 DMA descriptor read back to make sure data and desc synchronization.
0075
0076 intel,dma-dburst-wr:
0077 type: boolean
0078 description:
0079 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
0080 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
0081 It only applies to RX DMA and memcopy DMA.
0082
0083 required:
0084 - compatible
0085 - reg
0086
0087 additionalProperties: false
0088
0089 examples:
0090 - |
0091 dma0: dma-controller@e0e00000 {
0092 compatible = "intel,lgm-cdma";
0093 reg = <0xe0e00000 0x1000>;
0094 #dma-cells = <3>;
0095 dma-channels = <16>;
0096 dma-channel-mask = <0xFFFF>;
0097 interrupt-parent = <&ioapic1>;
0098 interrupts = <82 1>;
0099 resets = <&rcu0 0x30 0>;
0100 reset-names = "ctrl";
0101 clocks = <&cgu0 80>;
0102 intel,dma-poll-cnt = <4>;
0103 intel,dma-byte-en;
0104 intel,dma-drb;
0105 };
0106 - |
0107 dma3: dma-controller@ec800000 {
0108 compatible = "intel,lgm-dma3";
0109 reg = <0xec800000 0x1000>;
0110 clocks = <&cgu0 71>;
0111 resets = <&rcu0 0x10 9>;
0112 #dma-cells = <3>;
0113 intel,dma-poll-cnt = <16>;
0114 intel,dma-byte-en;
0115 intel,dma-dburst-wr;
0116 };
