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OSCL-LXR

 
 

    


0001 NXP Layerscape SoC qDMA Controller
0002 ==================================
0003 
0004 This device follows the generic DMA bindings defined in dma/dma.txt.
0005 
0006 Required properties:
0007 
0008 - compatible:           Must be one of
0009                          "fsl,ls1021a-qdma": for LS1021A Board
0010                          "fsl,ls1028a-qdma": for LS1028A Board
0011                          "fsl,ls1043a-qdma": for ls1043A Board
0012                          "fsl,ls1046a-qdma": for ls1046A Board
0013 - reg:                  Should contain the register's base address and length.
0014 - interrupts:           Should contain a reference to the interrupt used by this
0015                         device.
0016 - interrupt-names:      Should contain interrupt names:
0017                          "qdma-queue0": the block0 interrupt
0018                          "qdma-queue1": the block1 interrupt
0019                          "qdma-queue2": the block2 interrupt
0020                          "qdma-queue3": the block3 interrupt
0021                          "qdma-error":  the error interrupt
0022 - fsl,dma-queues:       Should contain number of queues supported.
0023 - dma-channels: Number of DMA channels supported
0024 - block-number: the virtual block number
0025 - block-offset: the offset of different virtual block
0026 - status-sizes: status queue size of per virtual block
0027 - queue-sizes:          command queue size of per virtual block, the size number
0028                         based on queues
0029 
0030 Optional properties:
0031 
0032 - dma-channels:         Number of DMA channels supported by the controller.
0033 - big-endian:           If present registers and hardware scatter/gather descriptors
0034                         of the qDMA are implemented in big endian mode, otherwise in little
0035                         mode.
0036 
0037 Examples:
0038 
0039         qdma: dma-controller@8390000 {
0040                         compatible = "fsl,ls1021a-qdma";
0041                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
0042                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
0043                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
0044                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0045                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0046                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0047                         interrupt-names = "qdma-error",
0048                                 "qdma-queue0", "qdma-queue1";
0049                         dma-channels = <8>;
0050                         block-number = <2>;
0051                         block-offset = <0x1000>;
0052                         fsl,dma-queues = <2>;
0053                         status-sizes = <64>;
0054                         queue-sizes = <64 64>;
0055                         big-endian;
0056                 };
0057 
0058 DMA clients must use the format described in dma/dma.txt file.