0001 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
0002
0003 Required properties:
0004 - compatible : Should be one of
0005 "fsl,imx25-sdma"
0006 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
0007 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
0008 "fsl,imx51-sdma"
0009 "fsl,imx53-sdma"
0010 "fsl,imx6q-sdma"
0011 "fsl,imx7d-sdma"
0012 "fsl,imx6ul-sdma"
0013 "fsl,imx8mq-sdma"
0014 "fsl,imx8mm-sdma"
0015 "fsl,imx8mn-sdma"
0016 "fsl,imx8mp-sdma"
0017 The -to variants should be preferred since they allow to determine the
0018 correct ROM script addresses needed for the driver to work without additional
0019 firmware.
0020 - reg : Should contain SDMA registers location and length
0021 - interrupts : Should contain SDMA interrupt
0022 - #dma-cells : Must be <3>.
0023 The first cell specifies the DMA request/event ID. See details below
0024 about the second and third cell.
0025 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
0026 scripts firmware
0027
0028 The second cell of dma phandle specifies the peripheral type of DMA transfer.
0029 The full ID of peripheral types can be found below.
0030
0031 ID transfer type
0032 ---------------------
0033 0 MCU domain SSI
0034 1 Shared SSI
0035 2 MMC
0036 3 SDHC
0037 4 MCU domain UART
0038 5 Shared UART
0039 6 FIRI
0040 7 MCU domain CSPI
0041 8 Shared CSPI
0042 9 SIM
0043 10 ATA
0044 11 CCM
0045 12 External peripheral
0046 13 Memory Stick Host Controller
0047 14 Shared Memory Stick Host Controller
0048 15 DSP
0049 16 Memory
0050 17 FIFO type Memory
0051 18 SPDIF
0052 19 IPU Memory
0053 20 ASRC
0054 21 ESAI
0055 22 SSI Dual FIFO (needs firmware ver >= 2)
0056 23 Shared ASRC
0057 24 SAI
0058
0059 The third cell specifies the transfer priority as below.
0060
0061 ID transfer priority
0062 -------------------------
0063 0 High
0064 1 Medium
0065 2 Low
0066
0067 Optional properties:
0068
0069 - gpr : The phandle to the General Purpose Register (GPR) node.
0070 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
0071 <reg shift val>.
0072 reg is the GPR register offset.
0073 shift is the bit position inside the GPR register.
0074 val is the value of the bit (0 or 1).
0075
0076 Examples:
0077
0078 sdma@83fb0000 {
0079 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
0080 reg = <0x83fb0000 0x4000>;
0081 interrupts = <6>;
0082 #dma-cells = <3>;
0083 fsl,sdma-ram-script-name = "sdma-imx51.bin";
0084 };
0085
0086 DMA clients connected to the i.MX SDMA controller must use the format
0087 described in the dma.txt file.
0088
0089 Examples:
0090
0091 ssi2: ssi@70014000 {
0092 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
0093 reg = <0x70014000 0x4000>;
0094 interrupts = <30>;
0095 clocks = <&clks 49>;
0096 dmas = <&sdma 24 1 0>,
0097 <&sdma 25 1 0>;
0098 dma-names = "rx", "tx";
0099 fsl,fifo-depth = <15>;
0100 };
0101
0102 Using the fsl,sdma-event-remap property:
0103
0104 If we want to use SDMA on the SAI1 port on a MX6SX:
0105
0106 &sdma {
0107 gpr = <&gpr>;
0108 /* SDMA events remap for SAI1_RX and SAI1_TX */
0109 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
0110 };
0111
0112 The fsl,sdma-event-remap property in this case has two values:
0113 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
0114 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
0115 Setting bit 15 to 1 selects SAI1_RX.
0116 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
0117 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
0118 Setting bit 16 to 1 selects SAI1_TX.
