0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale enhanced Direct Memory Access(eDMA) Controller
0008
0009 description: |
0010 The eDMA channels have multiplex capability by programmable
0011 memory-mapped registers. channels are split into two groups, called
0012 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
0013 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
0014
0015 maintainers:
0016 - Peng Fan <peng.fan@nxp.com>
0017
0018 properties:
0019 compatible:
0020 oneOf:
0021 - enum:
0022 - fsl,vf610-edma
0023 - fsl,imx7ulp-edma
0024 - items:
0025 - const: fsl,ls1028a-edma
0026 - const: fsl,vf610-edma
0027
0028 reg:
0029 minItems: 2
0030 maxItems: 3
0031
0032 interrupts:
0033 minItems: 2
0034 maxItems: 17
0035
0036 interrupt-names:
0037 minItems: 2
0038 maxItems: 17
0039
0040 "#dma-cells":
0041 const: 2
0042
0043 dma-channels:
0044 const: 32
0045
0046 clocks:
0047 maxItems: 2
0048
0049 clock-names:
0050 maxItems: 2
0051
0052 big-endian:
0053 description: |
0054 If present registers and hardware scatter/gather descriptors of the
0055 eDMA are implemented in big endian mode, otherwise in little mode.
0056 type: boolean
0057
0058 required:
0059 - "#dma-cells"
0060 - compatible
0061 - reg
0062 - interrupts
0063 - clocks
0064 - dma-channels
0065
0066 allOf:
0067 - $ref: "dma-controller.yaml#"
0068 - if:
0069 properties:
0070 compatible:
0071 contains:
0072 const: fsl,vf610-edma
0073 then:
0074 properties:
0075 clock-names:
0076 items:
0077 - const: dmamux0
0078 - const: dmamux1
0079 interrupts:
0080 maxItems: 2
0081 interrupt-names:
0082 items:
0083 - const: edma-tx
0084 - const: edma-err
0085 reg:
0086 maxItems: 3
0087
0088 - if:
0089 properties:
0090 compatible:
0091 contains:
0092 const: fsl,imx7ulp-edma
0093 then:
0094 properties:
0095 clock-names:
0096 items:
0097 - const: dma
0098 - const: dmamux0
0099 interrupts:
0100 maxItems: 17
0101 reg:
0102 maxItems: 2
0103
0104 unevaluatedProperties: false
0105
0106 examples:
0107 - |
0108 #include <dt-bindings/interrupt-controller/arm-gic.h>
0109 #include <dt-bindings/clock/vf610-clock.h>
0110
0111 edma0: dma-controller@40018000 {
0112 #dma-cells = <2>;
0113 compatible = "fsl,vf610-edma";
0114 reg = <0x40018000 0x2000>,
0115 <0x40024000 0x1000>,
0116 <0x40025000 0x1000>;
0117 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
0118 <0 9 IRQ_TYPE_LEVEL_HIGH>;
0119 interrupt-names = "edma-tx", "edma-err";
0120 dma-channels = <32>;
0121 clock-names = "dmamux0", "dmamux1";
0122 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
0123 };
0124
0125 - |
0126 #include <dt-bindings/interrupt-controller/arm-gic.h>
0127 #include <dt-bindings/clock/imx7ulp-clock.h>
0128
0129 edma1: dma-controller@40080000 {
0130 #dma-cells = <2>;
0131 compatible = "fsl,imx7ulp-edma";
0132 reg = <0x40080000 0x2000>,
0133 <0x40210000 0x1000>;
0134 dma-channels = <32>;
0135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0137 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0138 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0141 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0142 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0151 /* last is eDMA2-ERR interrupt */
0152 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0153 clock-names = "dma", "dmamux0";
0154 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
0155 };
