0001 * Atmel Extensible Direct Memory Access Controller (XDMAC)
0002
0003 * XDMA Controller
0004 Required properties:
0005 - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
0006 "microchip,sama7g5-dma".
0007 - reg: Should contain DMA registers location and length.
0008 - interrupts: Should contain DMA interrupt.
0009 - #dma-cells: Must be <1>, used to represent the number of integer cells in
0010 the dmas property of client devices.
0011 - The 1st cell specifies the channel configuration register:
0012 - bit 13: SIF, source interface identifier, used to get the memory
0013 interface identifier,
0014 - bit 14: DIF, destination interface identifier, used to get the peripheral
0015 interface identifier,
0016 - bit 30-24: PERID, peripheral identifier.
0017
0018 Example:
0019
0020 dma1: dma-controller@f0004000 {
0021 compatible = "atmel,sama5d4-dma";
0022 reg = <0xf0004000 0x200>;
0023 interrupts = <50 4 0>;
0024 #dma-cells = <1>;
0025 };
0026
0027
0028 * DMA clients
0029 DMA clients connected to the Atmel XDMA controller must use the format
0030 described in the dma.txt file, using a one-cell specifier for each channel.
0031 The two cells in order are:
0032 1. A phandle pointing to the DMA controller.
0033 2. Channel configuration register. Configurable fields are:
0034 - bit 13: SIF, source interface identifier, used to get the memory
0035 interface identifier,
0036 - bit 14: DIF, destination interface identifier, used to get the peripheral
0037 interface identifier,
0038 - bit 30-24: PERID, peripheral identifier.
0039
0040 Example:
0041
0042 i2c2: i2c@f8024000 {
0043 compatible = "atmel,at91sam9x5-i2c";
0044 reg = <0xf8024000 0x4000>;
0045 interrupts = <34 4 6>;
0046 dmas = <&dma1
0047 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
0048 | AT91_XDMAC_DT_PERID(6))>,
0049 <&dma1
0050 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
0051 | AT91_XDMAC_DT_PERID(7))>;
0052 dma-names = "tx", "rx";
0053 };
