bindings/dma/arm-pl08x.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
0008
0009 maintainers:
0010   - Vinod Koul <vkoul@kernel.org>
0011
0012 allOf:
0013   - $ref: /schemas/arm/primecell.yaml#
0014   - $ref: "dma-controller.yaml#"
0015
0016 # We need a select here so we don't match all nodes with 'arm,primecell'
0017 select:
0018   properties:
0019     compatible:
0020       contains:
0021         enum:
0022           - arm,pl080
0023           - arm,pl081
0024   required:
0025     - compatible
0026
0027 properties:
0028   compatible:
0029     oneOf:
0030       - items:
0031           - enum:
0032               - arm,pl080
0033               - arm,pl081
0034           - const: arm,primecell
0035       - items:
0036           - const: faraday,ftdma020
0037           - const: arm,pl080
0038           - const: arm,primecell
0039
0040   reg:
0041     maxItems: 1
0042     description: Address range of the PL08x registers
0043
0044   interrupts:
0045     minItems: 1
0046     description: The PL08x interrupt number
0047
0048   clocks:
0049     minItems: 1
0050     description: The clock running the IP core clock
0051
0052   clock-names:
0053     maxItems: 1
0054
0055   lli-bus-interface-ahb1:
0056     type: boolean
0057     description: if AHB master 1 is eligible for fetching LLIs
0058
0059   lli-bus-interface-ahb2:
0060     type: boolean
0061     description: if AHB master 2 is eligible for fetching LLIs
0062
0063   mem-bus-interface-ahb1:
0064     type: boolean
0065     description: if AHB master 1 is eligible for fetching memory contents
0066
0067   mem-bus-interface-ahb2:
0068     type: boolean
0069     description: if AHB master 2 is eligible for fetching memory contents
0070
0071   memcpy-burst-size:
0072     $ref: /schemas/types.yaml#/definitions/uint32
0073     enum:
0074       - 1
0075       - 4
0076       - 8
0077       - 16
0078       - 32
0079       - 64
0080       - 128
0081       - 256
0082     description: the size of the bursts for memcpy
0083
0084   memcpy-bus-width:
0085     $ref: /schemas/types.yaml#/definitions/uint32
0086     enum:
0087       - 8
0088       - 16
0089       - 32
0090       - 64
0091     description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
0092
0093   resets:
0094     maxItems: 1
0095
0096 required:
0097   - reg
0098   - interrupts
0099   - clocks
0100   - clock-names
0101   - "#dma-cells"
0102
0103 unevaluatedProperties: false
0104
0105 examples:
0106   - |
0107     dmac0: dma-controller@10130000 {
0108       compatible = "arm,pl080", "arm,primecell";
0109       reg = <0x10130000 0x1000>;
0110       interrupt-parent = <&vica>;
0111       interrupts = <15>;
0112       clocks = <&hclkdma0>;
0113       clock-names = "apb_pclk";
0114       lli-bus-interface-ahb1;
0115       lli-bus-interface-ahb2;
0116       mem-bus-interface-ahb2;
0117       memcpy-burst-size = <256>;
0118       memcpy-bus-width = <32>;
0119       #dma-cells = <2>;
0120     };
0121   - |
0122     #include <dt-bindings/interrupt-controller/irq.h>
0123     #include <dt-bindings/reset/cortina,gemini-reset.h>
0124     #include <dt-bindings/clock/cortina,gemini-clock.h>
0125     dma-controller@67000000 {
0126       compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
0127       /* Faraday Technology FTDMAC020 variant */
0128       arm,primecell-periphid = <0x0003b080>;
0129       reg = <0x67000000 0x1000>;
0130       interrupts = <9 IRQ_TYPE_EDGE_RISING>;
0131       resets = <&syscon GEMINI_RESET_DMAC>;
0132       clocks = <&syscon GEMINI_CLK_AHB>;
0133       clock-names = "apb_pclk";
0134       /* Bus interface AHB1 (AHB0) is totally tilted */
0135       lli-bus-interface-ahb2;
0136       mem-bus-interface-ahb2;
0137       memcpy-burst-size = <256>;
0138       memcpy-bus-width = <32>;
0139       #dma-cells = <2>;
0140     };