0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Altera mSGDMA IP core
0008
0009 maintainers:
0010 - Olivier Dautricourt <olivierdautricourt@gmail.com>
0011
0012 description: |
0013 Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
0014 intellectual property (IP)
0015
0016 allOf:
0017 - $ref: "dma-controller.yaml#"
0018
0019 properties:
0020 compatible:
0021 const: altr,socfpga-msgdma
0022
0023 reg:
0024 items:
0025 - description: Control and Status Register Slave Port
0026 - description: Descriptor Slave Port
0027 - description: Response Slave Port (Optional)
0028 minItems: 2
0029
0030 reg-names:
0031 items:
0032 - const: csr
0033 - const: desc
0034 - const: resp
0035 minItems: 2
0036
0037 interrupts:
0038 maxItems: 1
0039
0040 "#dma-cells":
0041 const: 1
0042 description:
0043 The cell identifies the channel id (must be 0)
0044
0045 required:
0046 - compatible
0047 - reg
0048 - reg-names
0049 - interrupts
0050
0051 unevaluatedProperties: false
0052
0053 examples:
0054 - |
0055 #include <dt-bindings/interrupt-controller/irq.h>
0056
0057 msgdma_controller: dma-controller@ff200b00 {
0058 compatible = "altr,socfpga-msgdma";
0059 reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
0060 reg-names = "csr", "desc", "resp";
0061 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
0062 #dma-cells = <1>;
0063 };
