0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx ZynqMP DisplayPort Subsystem
0008
0009 description: |
0010 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
0011 implements the display and audio pipelines based on the DisplayPort v1.2
0012 standard. The subsystem includes multiple functional blocks as below:
0013
0014 +------------------------------------------------------------+
0015 +--------+ | +----------------+ +-----------+ |
0016 | DPDMA | --->| | --> | Video | Video +-------------+ |
0017 | 4x vid | | | | | Rendering | -+--> | | | +------+
0018 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
0019 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
0020 | | and STC | +-----------+ | | Controller | | +------+
0021 Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
0022 | | | | Mixer | --+-> | | | +------+
0023 Live Audio --->| | --> | | || +-------------+ |
0024 | +----------------+ +-----------+ || |
0025 +---------------------------------------||-------------------+
0026 vv
0027 Blended Video and
0028 Mixed Audio to PL
0029
0030 The Buffer Manager interacts with external interface such as DMA engines or
0031 live audio/video streams from the programmable logic. The Video Rendering
0032 Pipeline blends the video and graphics layers and performs colorspace
0033 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
0034 Source Controller handles the DisplayPort protocol and connects to external
0035 PHYs.
0036
0037 The subsystem supports 2 video and 2 audio streams, and various pixel formats
0038 and depths up to 4K@30 resolution.
0039
0040 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
0041 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
0042 for more details.
0043
0044 maintainers:
0045 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0046
0047 properties:
0048 compatible:
0049 const: xlnx,zynqmp-dpsub-1.7
0050
0051 reg:
0052 maxItems: 4
0053 reg-names:
0054 items:
0055 - const: dp
0056 - const: blend
0057 - const: av_buf
0058 - const: aud
0059
0060 interrupts:
0061 maxItems: 1
0062
0063 clocks:
0064 description:
0065 The APB clock and at least one video clock are mandatory, the audio clock
0066 is optional.
0067 minItems: 2
0068 items:
0069 - description: dp_apb_clk is the APB clock
0070 - description: dp_aud_clk is the Audio clock
0071 - description:
0072 dp_vtc_pixel_clk_in is the non-live video clock (from Processing
0073 System)
0074 - description:
0075 dp_live_video_in_clk is the live video clock (from Programmable
0076 Logic)
0077 clock-names:
0078 oneOf:
0079 - minItems: 2
0080 items:
0081 - const: dp_apb_clk
0082 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
0083 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
0084 - minItems: 3
0085 items:
0086 - const: dp_apb_clk
0087 - const: dp_aud_clk
0088 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
0089 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
0090
0091 power-domains:
0092 maxItems: 1
0093
0094 resets:
0095 maxItems: 1
0096
0097 dmas:
0098 items:
0099 - description: Video layer, plane 0 (RGB or luma)
0100 - description: Video layer, plane 1 (U/V or U)
0101 - description: Video layer, plane 2 (V)
0102 - description: Graphics layer
0103 dma-names:
0104 items:
0105 - const: vid0
0106 - const: vid1
0107 - const: vid2
0108 - const: gfx0
0109
0110 phys:
0111 description: PHYs for the DP data lanes
0112 minItems: 1
0113 maxItems: 2
0114 phy-names:
0115 minItems: 1
0116 items:
0117 - const: dp-phy0
0118 - const: dp-phy1
0119
0120 required:
0121 - compatible
0122 - reg
0123 - reg-names
0124 - interrupts
0125 - clocks
0126 - clock-names
0127 - power-domains
0128 - resets
0129 - dmas
0130 - dma-names
0131 - phys
0132 - phy-names
0133
0134 additionalProperties: false
0135
0136 examples:
0137 - |
0138 #include <dt-bindings/phy/phy.h>
0139 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
0140
0141 display@fd4a0000 {
0142 compatible = "xlnx,zynqmp-dpsub-1.7";
0143 reg = <0xfd4a0000 0x1000>,
0144 <0xfd4aa000 0x1000>,
0145 <0xfd4ab000 0x1000>,
0146 <0xfd4ac000 0x1000>;
0147 reg-names = "dp", "blend", "av_buf", "aud";
0148 interrupts = <0 119 4>;
0149 interrupt-parent = <&gic>;
0150
0151 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
0152 clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
0153
0154 power-domains = <&pd_dp>;
0155 resets = <&reset ZYNQMP_RESET_DP>;
0156
0157 dma-names = "vid0", "vid1", "vid2", "gfx0";
0158 dmas = <&xlnx_dpdma 0>,
0159 <&xlnx_dpdma 1>,
0160 <&xlnx_dpdma 2>,
0161 <&xlnx_dpdma 3>;
0162
0163 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
0164 <&psgtr 0 PHY_TYPE_DP 1 3>;
0165
0166 phy-names = "dp-phy0", "dp-phy1";
0167 };
0168
0169 ...
