0001 Texas Instruments OMAP Display Subsystem
0002 ========================================
0003
0004 Generic Description
0005 -------------------
0006
0007 This document is a generic description of the OMAP Display Subsystem bindings.
0008 Binding details for each OMAP SoC version are described in respective binding
0009 documentation.
0010
0011 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
0012 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
0013 the encoder modules vary.
0014
0015 The DSS Core is the parent of the other DSS modules, and manages clock routing,
0016 integration to the SoC, etc.
0017
0018 DISPC is the display controller, which reads pixels from the memory and outputs
0019 a RGB pixel stream to encoders.
0020
0021 The encoder modules encode the received RGB pixel stream to a video output like
0022 HDMI, MIPI DPI, etc.
0023
0024 Video Ports
0025 -----------
0026
0027 The DSS Core and the encoders have video port outputs. The structure of the
0028 video ports is described in Documentation/devicetree/bindings/graph.txt,
0029 and the properties for the ports and endpoints for each encoder are
0030 described in the SoC's DSS binding documentation.
0031
0032 The video ports are used to describe the connections to external hardware, like
0033 panels or external encoders.
0034
0035 Aliases
0036 -------
0037
0038 The board dts file may define aliases for displays to assign "displayX" style
0039 name for each display. If no aliases are defined, a semi-random number is used
0040 for the display.
0041
0042 Example
0043 -------
0044
0045 A shortened example of the DSS description for OMAP4, with non-relevant parts
0046 removed, defined in omap4.dtsi:
0047
0048 dss: dss@58000000 {
0049 compatible = "ti,omap4-dss";
0050 reg = <0x58000000 0x80>;
0051 status = "disabled";
0052 ti,hwmods = "dss_core";
0053 clocks = <&dss_dss_clk>;
0054 clock-names = "fck";
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 ranges;
0058
0059 dispc@58001000 {
0060 compatible = "ti,omap4-dispc";
0061 reg = <0x58001000 0x1000>;
0062 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0063 ti,hwmods = "dss_dispc";
0064 clocks = <&dss_dss_clk>;
0065 clock-names = "fck";
0066 };
0067
0068 hdmi: encoder@58006000 {
0069 compatible = "ti,omap4-hdmi";
0070 reg = <0x58006000 0x200>,
0071 <0x58006200 0x100>,
0072 <0x58006300 0x100>,
0073 <0x58006400 0x1000>;
0074 reg-names = "wp", "pll", "phy", "core";
0075 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0076 status = "disabled";
0077 ti,hwmods = "dss_hdmi";
0078 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
0079 clock-names = "fck", "sys_clk";
0080 };
0081 };
0082
0083 A shortened example of the board description for OMAP4 Panda board, defined in
0084 omap4-panda.dts.
0085
0086 The Panda board has a DVI and a HDMI connector, and the board contains a TFP410
0087 chip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
0088 shifter). The video pipelines for the connectors are formed as follows:
0089
0090 DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
0091 OMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector
0092
0093 / {
0094 aliases {
0095 display0 = &dvi0;
0096 display1 = &hdmi0;
0097 };
0098
0099 tfp410: encoder@0 {
0100 compatible = "ti,tfp410";
0101 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */
0102
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&tfp410_pins>;
0105
0106 ports {
0107 #address-cells = <1>;
0108 #size-cells = <0>;
0109
0110 port@0 {
0111 reg = <0>;
0112
0113 tfp410_in: endpoint@0 {
0114 remote-endpoint = <&dpi_out>;
0115 };
0116 };
0117
0118 port@1 {
0119 reg = <1>;
0120
0121 tfp410_out: endpoint@0 {
0122 remote-endpoint = <&dvi_connector_in>;
0123 };
0124 };
0125 };
0126 };
0127
0128 dvi0: connector@0 {
0129 compatible = "dvi-connector";
0130 label = "dvi";
0131
0132 i2c-bus = <&i2c3>;
0133
0134 port {
0135 dvi_connector_in: endpoint {
0136 remote-endpoint = <&tfp410_out>;
0137 };
0138 };
0139 };
0140
0141 tpd12s015: encoder@1 {
0142 compatible = "ti,tpd12s015";
0143
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&tpd12s015_pins>;
0146
0147 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
0148 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
0149 <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
0150
0151 ports {
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154
0155 port@0 {
0156 reg = <0>;
0157
0158 tpd12s015_in: endpoint@0 {
0159 remote-endpoint = <&hdmi_out>;
0160 };
0161 };
0162
0163 port@1 {
0164 reg = <1>;
0165
0166 tpd12s015_out: endpoint@0 {
0167 remote-endpoint = <&hdmi_connector_in>;
0168 };
0169 };
0170 };
0171 };
0172
0173 hdmi0: connector@1 {
0174 compatible = "hdmi-connector";
0175 label = "hdmi";
0176
0177 port {
0178 hdmi_connector_in: endpoint {
0179 remote-endpoint = <&tpd12s015_out>;
0180 };
0181 };
0182 };
0183 };
0184
0185 &dss {
0186 status = "ok";
0187
0188 pinctrl-names = "default";
0189 pinctrl-0 = <&dss_dpi_pins>;
0190
0191 port {
0192 dpi_out: endpoint {
0193 remote-endpoint = <&tfp410_in>;
0194 data-lines = <24>;
0195 };
0196 };
0197 };
0198
0199 &hdmi {
0200 status = "ok";
0201 vdda-supply = <&vdac>;
0202
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&dss_hdmi_pins>;
0205
0206 port {
0207 hdmi_out: endpoint {
0208 remote-endpoint = <&tpd12s015_in>;
0209 };
0210 };
0211 };
