display/tegra/nvidia%2Ctegra20-vi.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Video Input controller
0008
0009 maintainers:
0010   - Thierry Reding <thierry.reding@gmail.com>
0011   - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014   $nodename:
0015     pattern: "^vi@[0-9a-f]+$"
0016
0017   compatible:
0018     oneOf:
0019       - const: nvidia,tegra20-vi
0020       - const: nvidia,tegra30-vi
0021       - const: nvidia,tegra114-vi
0022       - const: nvidia,tegra124-vi
0023       - items:
0024           - const: nvidia,tegra132-vi
0025           - const: nvidia,tegra124-vi
0026       - const: nvidia,tegra210-vi
0027       - const: nvidia,tegra186-vi
0028       - const: nvidia,tegra194-vi
0029
0030   reg:
0031     maxItems: 1
0032
0033   interrupts:
0034     maxItems: 1
0035
0036   clocks:
0037     maxItems: 1
0038
0039   resets:
0040     items:
0041       - description: module reset
0042
0043   reset-names:
0044     items:
0045       - const: vi
0046
0047   iommus:
0048     maxItems: 1
0049
0050   interconnects:
0051     minItems: 4
0052     maxItems: 5
0053
0054   interconnect-names:
0055     minItems: 4
0056     maxItems: 5
0057
0058   operating-points-v2:
0059     $ref: "/schemas/types.yaml#/definitions/phandle"
0060
0061   power-domains:
0062     items:
0063       - description: phandle to the VENC power domain
0064
0065   "#address-cells":
0066     const: 1
0067
0068   "#size-cells":
0069     const: 1
0070
0071   ranges:
0072     maxItems: 1
0073
0074   avdd-dsi-csi-supply:
0075     description: DSI/CSI power supply. Must supply 1.2 V.
0076
0077 patternProperties:
0078   "^csi@[0-9a-f]+$":
0079     type: object
0080
0081 additionalProperties: false
0082
0083 required:
0084   - compatible
0085   - reg
0086   - interrupts
0087   - clocks
0088
0089 allOf:
0090   - if:
0091       properties:
0092         compatible:
0093           contains:
0094             enum:
0095               - nvidia,tegra20-vi
0096               - nvidia,tegra30-vi
0097               - nvidia,tegra114-vi
0098               - nvidia,tegra124-vi
0099     then:
0100       required:
0101         - resets
0102         - reset-names
0103     else:
0104       required:
0105         - power-domains
0106
0107 examples:
0108   - |
0109     #include <dt-bindings/clock/tegra20-car.h>
0110     #include <dt-bindings/interrupt-controller/arm-gic.h>
0111
0112     vi@54080000 {
0113         compatible = "nvidia,tegra20-vi";
0114         reg = <0x54080000 0x00040000>;
0115         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0116         clocks = <&tegra_car TEGRA20_CLK_VI>;
0117         resets = <&tegra_car 100>;
0118         reset-names = "vi";
0119     };
0120
0121   - |
0122     #include <dt-bindings/clock/tegra210-car.h>
0123     #include <dt-bindings/interrupt-controller/arm-gic.h>
0124
0125     vi@54080000 {
0126         compatible = "nvidia,tegra210-vi";
0127         reg = <0x54080000 0x00000700>;
0128         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0129         assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
0130         assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
0131
0132         clocks = <&tegra_car TEGRA210_CLK_VI>;
0133         power-domains = <&pd_venc>;
0134
0135         #address-cells = <1>;
0136         #size-cells = <1>;
0137
0138         ranges = <0x0 0x54080000 0x2000>;
0139
0140         csi@838 {
0141             compatible = "nvidia,tegra210-csi";
0142             reg = <0x838 0x1300>;
0143             assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
0144                               <&tegra_car TEGRA210_CLK_CILCD>,
0145                               <&tegra_car TEGRA210_CLK_CILE>,
0146                               <&tegra_car TEGRA210_CLK_CSI_TPG>;
0147             assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
0148                                      <&tegra_car TEGRA210_CLK_PLL_P>,
0149                                      <&tegra_car TEGRA210_CLK_PLL_P>;
0150             assigned-clock-rates = <102000000>,
0151                                    <102000000>,
0152                                    <102000000>,
0153                                    <972000000>;
0154
0155             clocks = <&tegra_car TEGRA210_CLK_CSI>,
0156                      <&tegra_car TEGRA210_CLK_CILAB>,
0157                      <&tegra_car TEGRA210_CLK_CILCD>,
0158                      <&tegra_car TEGRA210_CLK_CILE>,
0159                      <&tegra_car TEGRA210_CLK_CSI_TPG>;
0160             clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
0161             power-domains = <&pd_sor>;
0162         };
0163     };