0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra TV Encoder Output
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^tvo@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra20-tvo
0020 - nvidia,tegra30-tvo
0021 - nvidia,tegra114-tvo
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 items:
0031 - description: module clock
0032
0033 operating-points-v2:
0034 $ref: "/schemas/types.yaml#/definitions/phandle"
0035
0036 power-domains:
0037 items:
0038 - description: phandle to the core power domain
0039
0040 additionalProperties: false
0041
0042 required:
0043 - compatible
0044 - reg
0045 - interrupts
0046 - clocks
0047
0048 examples:
0049 - |
0050 #include <dt-bindings/clock/tegra20-car.h>
0051 #include <dt-bindings/interrupt-controller/arm-gic.h>
0052
0053 tvo@542c0000 {
0054 compatible = "nvidia,tegra20-tvo";
0055 reg = <0x542c0000 0x00040000>;
0056 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0057 clocks = <&tegra_car TEGRA20_CLK_TVO>;
0058 };
