0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Video Encoder
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^mpe@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra20-mpe
0020 - nvidia,tegra30-mpe
0021 - nvidia,tegra114-mpe
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 items:
0031 - description: module clock
0032
0033 resets:
0034 items:
0035 - description: module reset
0036
0037 reset-names:
0038 items:
0039 - const: mpe
0040
0041 iommus:
0042 maxItems: 1
0043
0044 interconnects:
0045 minItems: 6
0046 maxItems: 6
0047
0048 interconnect-names:
0049 minItems: 6
0050 maxItems: 6
0051
0052 operating-points-v2:
0053 $ref: "/schemas/types.yaml#/definitions/phandle"
0054
0055 power-domains:
0056 items:
0057 - description: phandle to the MPE power domain
0058
0059 additionalProperties: false
0060
0061 examples:
0062 - |
0063 #include <dt-bindings/clock/tegra20-car.h>
0064 #include <dt-bindings/interrupt-controller/arm-gic.h>
0065
0066 mpe@54040000 {
0067 compatible = "nvidia,tegra20-mpe";
0068 reg = <0x54040000 0x00040000>;
0069 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0070 clocks = <&tegra_car TEGRA20_CLK_MPE>;
0071 resets = <&tegra_car 60>;
0072 reset-names = "mpe";
0073 };
