0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra ISP processor
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - nvidia,tegra20-isp
0017 - nvidia,tegra30-isp
0018 - nvidia,tegra210-isp
0019
0020 reg:
0021 maxItems: 1
0022
0023 interrupts:
0024 maxItems: 1
0025
0026 clocks:
0027 items:
0028 - description: module clock
0029
0030 resets:
0031 items:
0032 - description: module reset
0033
0034 reset-names:
0035 items:
0036 - const: isp
0037
0038 iommus:
0039 maxItems: 1
0040
0041 interconnects:
0042 items:
0043 - description: memory write client
0044
0045 interconnect-names:
0046 items:
0047 - const: dma-mem # write
0048
0049 power-domains:
0050 items:
0051 - description: phandle to the VENC or core power domain
0052
0053 additionalProperties: false
0054
0055 examples:
0056 - |
0057 #include <dt-bindings/clock/tegra20-car.h>
0058 #include <dt-bindings/interrupt-controller/arm-gic.h>
0059
0060 isp@54100000 {
0061 compatible = "nvidia,tegra20-isp";
0062 reg = <0x54100000 0x00040000>;
0063 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0064 clocks = <&tegra_car TEGRA20_CLK_ISP>;
0065 resets = <&tegra_car 23>;
0066 reset-names = "isp";
0067 };
