0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra host1x controller
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: The host1x top-level node defines a number of children, each
0014 representing one of the host1x client modules defined in this binding.
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - enum:
0020 - nvidia,tegra20-host1x
0021 - nvidia,tegra30-host1x
0022 - nvidia,tegra114-host1x
0023 - nvidia,tegra124-host1x
0024 - nvidia,tegra210-host1x
0025 - nvidia,tegra186-host1x
0026 - nvidia,tegra194-host1x
0027 - nvidia,tegra234-host1x
0028
0029 - items:
0030 - const: nvidia,tegra132-host1x
0031 - const: nvidia,tegra124-host1x
0032
0033 reg:
0034 minItems: 1
0035 maxItems: 3
0036
0037 reg-names:
0038 minItems: 1
0039 maxItems: 3
0040
0041 interrupts:
0042 minItems: 1
0043 maxItems: 9
0044
0045 interrupt-names:
0046 minItems: 1
0047 maxItems: 9
0048
0049 '#address-cells':
0050 description: The number of cells used to represent physical base addresses
0051 in the host1x address space.
0052 enum: [1, 2]
0053
0054 '#size-cells':
0055 description: The number of cells used to represent the size of an address
0056 range in the host1x address space.
0057 enum: [1, 2]
0058
0059 ranges:
0060 maxItems: 1
0061
0062 clocks:
0063 description: Must contain one entry, for the module clock. See
0064 ../clocks/clock-bindings.txt for details.
0065
0066 clock-names:
0067 items:
0068 - const: host1x
0069
0070 resets:
0071 minItems: 1 # MC reset is optional on Tegra186 and later
0072 items:
0073 - description: module reset
0074 - description: memory client hotflush reset
0075
0076 reset-names:
0077 minItems: 1 # MC reset is optional on Tegra186 and later
0078 items:
0079 - const: host1x
0080 - const: mc
0081
0082 iommus:
0083 maxItems: 1
0084
0085 interconnects:
0086 items:
0087 - description: memory read client for host1x
0088
0089 interconnect-names:
0090 items:
0091 - const: dma-mem # read
0092
0093 operating-points-v2:
0094 $ref: "/schemas/types.yaml#/definitions/phandle"
0095
0096 power-domains:
0097 items:
0098 - description: phandle to the HEG or core power domain
0099
0100 required:
0101 - compatible
0102 - interrupts
0103 - interrupt-names
0104 - '#address-cells'
0105 - '#size-cells'
0106 - ranges
0107 - reg
0108 - clocks
0109 - clock-names
0110
0111 unevaluatedProperties:
0112 type: object
0113
0114 allOf:
0115 - if:
0116 properties:
0117 compatible:
0118 contains:
0119 enum:
0120 - nvidia,tegra20-host1x
0121 - nvidia,tegra30-host1x
0122 - nvidia,tegra114-host1x
0123 - nvidia,tegra124-host1x
0124 - nvidia,tegra210-host1x
0125 then:
0126 properties:
0127 interrupts:
0128 items:
0129 - description: host1x syncpoint interrupt
0130 - description: host1x general interrupt
0131
0132 interrupt-names:
0133 items:
0134 - const: syncpt
0135 - const: host1x
0136 required:
0137 - resets
0138 - reset-names
0139 - if:
0140 properties:
0141 compatible:
0142 contains:
0143 enum:
0144 - nvidia,tegra186-host1x
0145 - nvidia,tegra194-host1x
0146 then:
0147 properties:
0148 reg-names:
0149 items:
0150 - const: hypervisor
0151 - const: vm
0152
0153 reg:
0154 items:
0155 - description: region used by the hypervisor
0156 - description: region assigned to the virtual machine
0157
0158 resets:
0159 maxItems: 1
0160
0161 reset-names:
0162 maxItems: 1
0163
0164 interrupts:
0165 items:
0166 - description: host1x syncpoint interrupt
0167 - description: host1x general interrupt
0168
0169 interrupt-names:
0170 items:
0171 - const: syncpt
0172 - const: host1x
0173
0174 iommu-map:
0175 description: Specification of stream IDs available for memory context device
0176 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
0177 usable stream IDs.
0178
0179 required:
0180 - reg-names
0181 - if:
0182 properties:
0183 compatible:
0184 contains:
0185 enum:
0186 - nvidia,tegra234-host1x
0187 then:
0188 properties:
0189 reg-names:
0190 items:
0191 - const: common
0192 - const: hypervisor
0193 - const: vm
0194
0195 reg:
0196 items:
0197 - description: region used by host1x server
0198 - description: region used by the hypervisor
0199 - description: region assigned to the virtual machine
0200
0201 interrupts:
0202 items:
0203 - description: host1x syncpoint interrupt 0
0204 - description: host1x syncpoint interrupt 1
0205 - description: host1x syncpoint interrupt 2
0206 - description: host1x syncpoint interrupt 3
0207 - description: host1x syncpoint interrupt 4
0208 - description: host1x syncpoint interrupt 5
0209 - description: host1x syncpoint interrupt 6
0210 - description: host1x syncpoint interrupt 7
0211 - description: host1x general interrupt
0212
0213 interrupt-names:
0214 items:
0215 - const: syncpt0
0216 - const: syncpt1
0217 - const: syncpt2
0218 - const: syncpt3
0219 - const: syncpt4
0220 - const: syncpt5
0221 - const: syncpt6
0222 - const: syncpt7
0223 - const: host1x
0224
0225 iommu-map:
0226 description: Specification of stream IDs available for memory context device
0227 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
0228 usable stream IDs.
0229
0230 required:
0231 - reg-names
0232
0233 examples:
0234 - |
0235 #include <dt-bindings/clock/tegra20-car.h>
0236 #include <dt-bindings/gpio/tegra-gpio.h>
0237 #include <dt-bindings/memory/tegra20-mc.h>
0238
0239 host1x@50000000 {
0240 compatible = "nvidia,tegra20-host1x";
0241 reg = <0x50000000 0x00024000>;
0242 interrupts = <0 65 0x04>, /* mpcore syncpt */
0243 <0 67 0x04>; /* mpcore general */
0244 interrupt-names = "syncpt", "host1x";
0245 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
0246 clock-names = "host1x";
0247 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
0248 reset-names = "host1x", "mc";
0249
0250 #address-cells = <1>;
0251 #size-cells = <1>;
0252
0253 ranges = <0x54000000 0x54000000 0x04000000>;
0254
0255 mpe@54040000 {
0256 compatible = "nvidia,tegra20-mpe";
0257 reg = <0x54040000 0x00040000>;
0258 interrupts = <0 68 0x04>;
0259 clocks = <&tegra_car TEGRA20_CLK_MPE>;
0260 resets = <&tegra_car 60>;
0261 reset-names = "mpe";
0262 };
0263
0264 vi@54080000 {
0265 compatible = "nvidia,tegra20-vi";
0266 reg = <0x54080000 0x00040000>;
0267 interrupts = <0 69 0x04>;
0268 clocks = <&tegra_car TEGRA20_CLK_VI>;
0269 resets = <&tegra_car 100>;
0270 reset-names = "vi";
0271 };
0272
0273 epp@540c0000 {
0274 compatible = "nvidia,tegra20-epp";
0275 reg = <0x540c0000 0x00040000>;
0276 interrupts = <0 70 0x04>;
0277 clocks = <&tegra_car TEGRA20_CLK_EPP>;
0278 resets = <&tegra_car 19>;
0279 reset-names = "epp";
0280 };
0281
0282 isp@54100000 {
0283 compatible = "nvidia,tegra20-isp";
0284 reg = <0x54100000 0x00040000>;
0285 interrupts = <0 71 0x04>;
0286 clocks = <&tegra_car TEGRA20_CLK_ISP>;
0287 resets = <&tegra_car 23>;
0288 reset-names = "isp";
0289 };
0290
0291 gr2d@54140000 {
0292 compatible = "nvidia,tegra20-gr2d";
0293 reg = <0x54140000 0x00040000>;
0294 interrupts = <0 72 0x04>;
0295 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
0296 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
0297 reset-names = "2d", "mc";
0298 };
0299
0300 gr3d@54180000 {
0301 compatible = "nvidia,tegra20-gr3d";
0302 reg = <0x54180000 0x00040000>;
0303 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
0304 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
0305 reset-names = "3d", "mc";
0306 };
0307
0308 dc@54200000 {
0309 compatible = "nvidia,tegra20-dc";
0310 reg = <0x54200000 0x00040000>;
0311 interrupts = <0 73 0x04>;
0312 clocks = <&tegra_car TEGRA20_CLK_DISP1>;
0313 clock-names = "dc";
0314 resets = <&tegra_car 27>;
0315 reset-names = "dc";
0316
0317 rgb {
0318 };
0319 };
0320
0321 dc@54240000 {
0322 compatible = "nvidia,tegra20-dc";
0323 reg = <0x54240000 0x00040000>;
0324 interrupts = <0 74 0x04>;
0325 clocks = <&tegra_car TEGRA20_CLK_DISP2>;
0326 clock-names = "dc";
0327 resets = <&tegra_car 26>;
0328 reset-names = "dc";
0329
0330 rgb {
0331 };
0332 };
0333
0334 hdmi@54280000 {
0335 compatible = "nvidia,tegra20-hdmi";
0336 reg = <0x54280000 0x00040000>;
0337 interrupts = <0 75 0x04>;
0338 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
0339 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
0340 clock-names = "hdmi", "parent";
0341 resets = <&tegra_car 51>;
0342 reset-names = "hdmi";
0343
0344 hdmi-supply = <&vdd_5v0_hdmi>;
0345 pll-supply = <&vdd_hdmi_pll>;
0346 vdd-supply = <&vdd_3v3_hdmi>;
0347
0348 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0349 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
0350 };
0351
0352 tvo@542c0000 {
0353 compatible = "nvidia,tegra20-tvo";
0354 reg = <0x542c0000 0x00040000>;
0355 interrupts = <0 76 0x04>;
0356 clocks = <&tegra_car TEGRA20_CLK_TVO>;
0357 };
0358
0359 dsi@54300000 {
0360 compatible = "nvidia,tegra20-dsi";
0361 reg = <0x54300000 0x00040000>;
0362 clocks = <&tegra_car TEGRA20_CLK_DSI>,
0363 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
0364 clock-names = "dsi", "parent";
0365 resets = <&tegra_car 48>;
0366 reset-names = "dsi";
0367 };
0368 };
0369
0370 - |
0371 #include <dt-bindings/clock/tegra210-car.h>
0372 #include <dt-bindings/interrupt-controller/arm-gic.h>
0373 #include <dt-bindings/memory/tegra210-mc.h>
0374
0375 host1x@50000000 {
0376 compatible = "nvidia,tegra210-host1x";
0377 reg = <0x50000000 0x00024000>;
0378 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
0379 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
0380 interrupt-names = "syncpt", "host1x";
0381 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
0382 clock-names = "host1x";
0383 resets = <&tegra_car 28>;
0384 reset-names = "host1x";
0385
0386 #address-cells = <1>;
0387 #size-cells = <1>;
0388
0389 ranges = <0x54000000 0x54000000 0x01000000>;
0390 iommus = <&mc TEGRA_SWGROUP_HC>;
0391
0392 vi@54080000 {
0393 compatible = "nvidia,tegra210-vi";
0394 reg = <0x54080000 0x00000700>;
0395 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0396 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
0397 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
0398
0399 clocks = <&tegra_car TEGRA210_CLK_VI>;
0400 power-domains = <&pd_venc>;
0401
0402 #address-cells = <1>;
0403 #size-cells = <1>;
0404
0405 ranges = <0x0 0x54080000 0x2000>;
0406
0407 csi@838 {
0408 compatible = "nvidia,tegra210-csi";
0409 reg = <0x838 0x1300>;
0410 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
0411 <&tegra_car TEGRA210_CLK_CILCD>,
0412 <&tegra_car TEGRA210_CLK_CILE>,
0413 <&tegra_car TEGRA210_CLK_CSI_TPG>;
0414 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
0415 <&tegra_car TEGRA210_CLK_PLL_P>,
0416 <&tegra_car TEGRA210_CLK_PLL_P>;
0417 assigned-clock-rates = <102000000>,
0418 <102000000>,
0419 <102000000>,
0420 <972000000>;
0421
0422 clocks = <&tegra_car TEGRA210_CLK_CSI>,
0423 <&tegra_car TEGRA210_CLK_CILAB>,
0424 <&tegra_car TEGRA210_CLK_CILCD>,
0425 <&tegra_car TEGRA210_CLK_CILE>,
0426 <&tegra_car TEGRA210_CLK_CSI_TPG>;
0427 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
0428 power-domains = <&pd_sor>;
0429 };
0430 };
0431 };
