0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA 2D graphics engine
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^gr2d@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra20-gr2d
0020 - nvidia,tegra30-gr2d
0021 - nvidia,tegra114-gr2d
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 items:
0031 - description: module clock
0032
0033 resets:
0034 items:
0035 - description: module reset
0036 - description: memory client hotflush reset
0037
0038 reset-names:
0039 items:
0040 - const: 2d
0041 - const: mc
0042
0043 iommus:
0044 maxItems: 1
0045
0046 interconnects:
0047 maxItems: 4
0048
0049 interconnect-names:
0050 maxItems: 4
0051
0052 operating-points-v2:
0053 $ref: "/schemas/types.yaml#/definitions/phandle"
0054
0055 power-domains:
0056 items:
0057 - description: phandle to the HEG or core power domain
0058
0059 additionalProperties: false
0060
0061 examples:
0062 - |
0063 #include <dt-bindings/clock/tegra20-car.h>
0064 #include <dt-bindings/interrupt-controller/arm-gic.h>
0065 #include <dt-bindings/memory/tegra20-mc.h>
0066
0067 gr2d@54140000 {
0068 compatible = "nvidia,tegra20-gr2d";
0069 reg = <0x54140000 0x00040000>;
0070 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0071 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
0072 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
0073 reset-names = "2d", "mc";
0074 };
