0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Encoder Pre-Processor
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^epp@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra20-epp
0020 - nvidia,tegra30-epp
0021 - nvidia,tegra114-epp
0022
0023 reg:
0024 maxItems: 1
0025
0026 interrupts:
0027 maxItems: 1
0028
0029 clocks:
0030 maxItems: 1
0031
0032 resets:
0033 items:
0034 - description: module reset
0035
0036 reset-names:
0037 items:
0038 - const: epp
0039
0040 iommus:
0041 maxItems: 1
0042
0043 interconnects:
0044 maxItems: 4
0045
0046 interconnect-names:
0047 maxItems: 4
0048
0049 operating-points-v2:
0050 $ref: "/schemas/types.yaml#/definitions/phandle"
0051
0052 power-domains:
0053 items:
0054 - description: phandle to the core power domain
0055
0056 additionalProperties: false
0057
0058 examples:
0059 - |
0060 #include <dt-bindings/clock/tegra20-car.h>
0061 #include <dt-bindings/interrupt-controller/arm-gic.h>
0062
0063 epp@540c0000 {
0064 compatible = "nvidia,tegra20-epp";
0065 reg = <0x540c0000 0x00040000>;
0066 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0067 clocks = <&tegra_car TEGRA20_CLK_EPP>;
0068 resets = <&tegra_car 19>;
0069 reset-names = "epp";
0070 };
