0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Display Serial Interface
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 compatible:
0015 oneOf:
0016 - enum:
0017 - nvidia,tegra20-dsi
0018 - nvidia,tegra30-dsi
0019 - nvidia,tegra114-dsi
0020 - nvidia,tegra124-dsi
0021 - nvidia,tegra210-dsi
0022 - nvidia,tegra186-dsi
0023
0024 - items:
0025 - const: nvidia,tegra132-dsi
0026 - const: nvidia,tegra124-dsi
0027
0028 reg:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 clocks:
0035 minItems: 2
0036 maxItems: 3
0037
0038 clock-names:
0039 minItems: 2
0040 maxItems: 3
0041
0042 resets:
0043 items:
0044 - description: module reset
0045
0046 reset-names:
0047 items:
0048 - const: dsi
0049
0050 operating-points-v2:
0051 $ref: "/schemas/types.yaml#/definitions/phandle"
0052
0053 power-domains:
0054 maxItems: 1
0055
0056 avdd-dsi-csi-supply:
0057 description: phandle of a supply that powers the DSI controller
0058
0059 nvidia,mipi-calibrate:
0060 description: Should contain a phandle and a specifier specifying
0061 which pads are used by this DSI output and need to be
0062 calibrated. See nvidia,tegra114-mipi.yaml for details.
0063 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0064
0065 nvidia,ddc-i2c-bus:
0066 description: phandle of an I2C controller used for DDC EDID
0067 probing
0068 $ref: "/schemas/types.yaml#/definitions/phandle"
0069
0070 nvidia,hpd-gpio:
0071 description: specifies a GPIO used for hotplug detection
0072 maxItems: 1
0073
0074 nvidia,edid:
0075 description: supplies a binary EDID blob
0076 $ref: "/schemas/types.yaml#/definitions/uint8-array"
0077
0078 nvidia,panel:
0079 description: phandle of a display panel
0080 $ref: "/schemas/types.yaml#/definitions/phandle"
0081
0082 nvidia,ganged-mode:
0083 description: contains a phandle to a second DSI controller to
0084 gang up with in order to support up to 8 data lanes
0085 $ref: "/schemas/types.yaml#/definitions/phandle"
0086
0087 allOf:
0088 - $ref: "../dsi-controller.yaml#"
0089 - if:
0090 properties:
0091 compatible:
0092 contains:
0093 enum:
0094 - nvidia,tegra20-dsi
0095 - nvidia,tegra30-dsi
0096 then:
0097 properties:
0098 clocks:
0099 items:
0100 - description: DSI module clock
0101 - description: input for the pixel clock
0102
0103 clock-names:
0104 items:
0105 - const: dsi
0106 - const: parent
0107 else:
0108 properties:
0109 clocks:
0110 items:
0111 - description: DSI module clock
0112 - description: low-power module clock
0113 - description: input for the pixel clock
0114
0115 clock-names:
0116 items:
0117 - const: dsi
0118 - const: lp
0119 - const: parent
0120
0121 - if:
0122 properties:
0123 compatible:
0124 contains:
0125 const: nvidia,tegra186-dsi
0126 then:
0127 required:
0128 - interrupts
0129
0130 unevaluatedProperties: false
0131
0132 required:
0133 - compatible
0134 - reg
0135 - clocks
0136 - clock-names
0137 - resets
0138 - reset-names
0139
0140 examples:
0141 - |
0142 #include <dt-bindings/clock/tegra186-clock.h>
0143 #include <dt-bindings/interrupt-controller/arm-gic.h>
0144 #include <dt-bindings/power/tegra186-powergate.h>
0145 #include <dt-bindings/reset/tegra186-reset.h>
0146
0147 dsi@15300000 {
0148 compatible = "nvidia,tegra186-dsi";
0149 reg = <0x15300000 0x10000>;
0150 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0151 clocks = <&bpmp TEGRA186_CLK_DSI>,
0152 <&bpmp TEGRA186_CLK_DSIA_LP>,
0153 <&bpmp TEGRA186_CLK_PLLD>;
0154 clock-names = "dsi", "lp", "parent";
0155 resets = <&bpmp TEGRA186_RESET_DSI>;
0156 reset-names = "dsi";
0157
0158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
0159 };
