0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra186 (and later) Display Hub
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^display-hub@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra186-display
0020 - nvidia,tegra194-display
0021
0022 '#address-cells':
0023 const: 1
0024
0025 '#size-cells':
0026 const: 1
0027
0028 reg:
0029 maxItems: 1
0030
0031 interrupts:
0032 maxItems: 1
0033
0034 clocks:
0035 minItems: 2
0036 maxItems: 3
0037
0038 clock-names:
0039 minItems: 2
0040 maxItems: 3
0041
0042 resets:
0043 items:
0044 - description: display hub reset
0045 - description: window group 0 reset
0046 - description: window group 1 reset
0047 - description: window group 2 reset
0048 - description: window group 3 reset
0049 - description: window group 4 reset
0050 - description: window group 5 reset
0051
0052 reset-names:
0053 items:
0054 - const: misc
0055 - const: wgrp0
0056 - const: wgrp1
0057 - const: wgrp2
0058 - const: wgrp3
0059 - const: wgrp4
0060 - const: wgrp5
0061
0062 power-domains:
0063 maxItems: 1
0064
0065 ranges:
0066 maxItems: 1
0067
0068 patternProperties:
0069 "^display@[0-9a-f]+$":
0070 type: object
0071
0072 allOf:
0073 - if:
0074 properties:
0075 compatible:
0076 contains:
0077 const: nvidia,tegra186-display
0078 then:
0079 properties:
0080 clocks:
0081 items:
0082 - description: display core clock
0083 - description: display stream compression clock
0084 - description: display hub clock
0085
0086 clock-names:
0087 items:
0088 - const: disp
0089 - const: dsc
0090 - const: hub
0091 else:
0092 properties:
0093 clocks:
0094 items:
0095 - description: display core clock
0096 - description: display hub clock
0097
0098 clock-names:
0099 items:
0100 - const: disp
0101 - const: hub
0102
0103 additionalProperties: false
0104
0105 required:
0106 - compatible
0107 - reg
0108 - clocks
0109 - clock-names
0110 - resets
0111 - reset-names
0112 - power-domains
0113 - "#address-cells"
0114 - "#size-cells"
0115 - ranges
0116
0117 examples:
0118 - |
0119 #include <dt-bindings/clock/tegra186-clock.h>
0120 #include <dt-bindings/interrupt-controller/arm-gic.h>
0121 #include <dt-bindings/memory/tegra186-mc.h>
0122 #include <dt-bindings/power/tegra186-powergate.h>
0123 #include <dt-bindings/reset/tegra186-reset.h>
0124
0125 display-hub@15200000 {
0126 compatible = "nvidia,tegra186-display";
0127 reg = <0x15200000 0x00040000>;
0128 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
0129 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
0130 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
0131 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
0132 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
0133 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
0134 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
0135 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
0136 "wgrp3", "wgrp4", "wgrp5";
0137 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
0138 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
0139 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
0140 clock-names = "disp", "dsc", "hub";
0141 status = "disabled";
0142
0143 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
0144
0145 #address-cells = <1>;
0146 #size-cells = <1>;
0147
0148 ranges = <0x15200000 0x15200000 0x40000>;
0149
0150 display@15200000 {
0151 compatible = "nvidia,tegra186-dc";
0152 reg = <0x15200000 0x10000>;
0153 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0154 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
0155 clock-names = "dc";
0156 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
0157 reset-names = "dc";
0158
0159 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
0160 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
0161 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0162 interconnect-names = "dma-mem", "read-1";
0163 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
0164
0165 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
0166 nvidia,head = <0>;
0167 };
0168
0169 display@15210000 {
0170 compatible = "nvidia,tegra186-dc";
0171 reg = <0x15210000 0x10000>;
0172 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0173 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
0174 clock-names = "dc";
0175 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
0176 reset-names = "dc";
0177
0178 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
0179 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
0180 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0181 interconnect-names = "dma-mem", "read-1";
0182 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
0183
0184 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
0185 nvidia,head = <1>;
0186 };
0187
0188 display@15220000 {
0189 compatible = "nvidia,tegra186-dc";
0190 reg = <0x15220000 0x10000>;
0191 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0192 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
0193 clock-names = "dc";
0194 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
0195 reset-names = "dc";
0196
0197 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
0198 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
0199 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0200 interconnect-names = "dma-mem", "read-1";
0201 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
0202
0203 nvidia,outputs = <&sor0 &sor1>;
0204 nvidia,head = <2>;
0205 };
0206 };
0207
0208 - |
0209 #include <dt-bindings/clock/tegra194-clock.h>
0210 #include <dt-bindings/interrupt-controller/arm-gic.h>
0211 #include <dt-bindings/memory/tegra194-mc.h>
0212 #include <dt-bindings/power/tegra194-powergate.h>
0213 #include <dt-bindings/reset/tegra194-reset.h>
0214
0215 display-hub@15200000 {
0216 compatible = "nvidia,tegra194-display";
0217 reg = <0x15200000 0x00040000>;
0218 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
0219 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
0220 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
0221 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
0222 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
0223 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
0224 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
0225 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
0226 "wgrp3", "wgrp4", "wgrp5";
0227 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
0228 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
0229 clock-names = "disp", "hub";
0230 status = "disabled";
0231
0232 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
0233
0234 #address-cells = <1>;
0235 #size-cells = <1>;
0236
0237 ranges = <0x15200000 0x15200000 0x40000>;
0238
0239 display@15200000 {
0240 compatible = "nvidia,tegra194-dc";
0241 reg = <0x15200000 0x10000>;
0242 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0243 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
0244 clock-names = "dc";
0245 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
0246 reset-names = "dc";
0247
0248 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
0249 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
0250 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0251 interconnect-names = "dma-mem", "read-1";
0252
0253 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
0254 nvidia,head = <0>;
0255 };
0256
0257 display@15210000 {
0258 compatible = "nvidia,tegra194-dc";
0259 reg = <0x15210000 0x10000>;
0260 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0261 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
0262 clock-names = "dc";
0263 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
0264 reset-names = "dc";
0265
0266 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
0267 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
0268 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0269 interconnect-names = "dma-mem", "read-1";
0270
0271 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
0272 nvidia,head = <1>;
0273 };
0274
0275 display@15220000 {
0276 compatible = "nvidia,tegra194-dc";
0277 reg = <0x15220000 0x10000>;
0278 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0279 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
0280 clock-names = "dc";
0281 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
0282 reset-names = "dc";
0283
0284 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
0285 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
0286 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0287 interconnect-names = "dma-mem", "read-1";
0288
0289 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
0290 nvidia,head = <2>;
0291 };
0292
0293 display@15230000 {
0294 compatible = "nvidia,tegra194-dc";
0295 reg = <0x15230000 0x10000>;
0296 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
0297 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
0298 clock-names = "dc";
0299 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
0300 reset-names = "dc";
0301
0302 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
0303 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
0304 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
0305 interconnect-names = "dma-mem", "read-1";
0306
0307 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
0308 nvidia,head = <3>;
0309 };
0310 };
