0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra186 (and later) Display Controller
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^display@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra186-dc
0020 - nvidia,tegra194-dc
0021
0022 reg:
0023 maxItems: 1
0024
0025 interrupts:
0026 maxItems: 1
0027
0028 clocks:
0029 items:
0030 - description: display controller pixel clock
0031
0032 clock-names:
0033 items:
0034 - const: dc
0035
0036 resets:
0037 items:
0038 - description: display controller reset
0039
0040 reset-names:
0041 items:
0042 - const: dc
0043
0044 power-domains:
0045 maxItems: 1
0046
0047 iommus:
0048 maxItems: 1
0049
0050 interconnects:
0051 description: Description of the interconnect paths for the
0052 display controller; see ../interconnect/interconnect.txt
0053 for details.
0054
0055 interconnect-names:
0056 items:
0057 - const: dma-mem # read-0
0058 - const: read-1
0059
0060 nvidia,outputs:
0061 description: A list of phandles of outputs that this display
0062 controller can drive.
0063 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0064
0065 nvidia,head:
0066 description: The number of the display controller head. This
0067 is used to setup the various types of output to receive
0068 video data from the given head.
0069 $ref: "/schemas/types.yaml#/definitions/uint32"
0070
0071 additionalProperties: false
0072
0073 required:
0074 - compatible
0075 - reg
0076 - interrupts
0077 - clocks
0078 - clock-names
0079 - resets
0080 - reset-names
0081 - power-domains
0082 - nvidia,outputs
0083 - nvidia,head
0084
0085 # see nvidia,tegra186-display.yaml for examples
