0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra SOR Output Encoder
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 description: |
0014 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
0015 and DP outputs.
0016
0017 properties:
0018 $nodename:
0019 pattern: "^sor@[0-9a-f]+$"
0020
0021 compatible:
0022 oneOf:
0023 - enum:
0024 - nvidia,tegra124-sor
0025 - nvidia,tegra210-sor
0026 - nvidia,tegra210-sor1
0027 - nvidia,tegra186-sor
0028 - nvidia,tegra186-sor1
0029 - nvidia,tegra194-sor
0030
0031 - items:
0032 - const: nvidia,tegra132-sor
0033 - const: nvidia,tegra124-sor
0034
0035 reg:
0036 maxItems: 1
0037
0038 interrupts:
0039 maxItems: 1
0040
0041 clocks:
0042 minItems: 5
0043 maxItems: 6
0044
0045 clock-names:
0046 minItems: 5
0047 maxItems: 6
0048
0049 resets:
0050 items:
0051 - description: module reset
0052
0053 reset-names:
0054 items:
0055 - const: sor
0056
0057 power-domains:
0058 maxItems: 1
0059
0060 avdd-io-hdmi-dp-supply:
0061 description: I/O supply for HDMI/DP
0062
0063 vdd-hdmi-dp-pll-supply:
0064 description: PLL supply for HDMI/DP
0065
0066 hdmi-supply:
0067 description: +5.0V HDMI connector supply, required for HDMI
0068
0069 # Tegra186 and later
0070 nvidia,interface:
0071 description: index of the SOR interface
0072 $ref: "/schemas/types.yaml#/definitions/uint32"
0073
0074 nvidia,ddc-i2c-bus:
0075 description: phandle of an I2C controller used for DDC EDID
0076 probing
0077 $ref: "/schemas/types.yaml#/definitions/phandle"
0078
0079 nvidia,hpd-gpio:
0080 description: specifies a GPIO used for hotplug detection
0081 maxItems: 1
0082
0083 nvidia,edid:
0084 description: supplies a binary EDID blob
0085 $ref: "/schemas/types.yaml#/definitions/uint8-array"
0086
0087 nvidia,panel:
0088 description: phandle of a display panel, required for eDP
0089 $ref: "/schemas/types.yaml#/definitions/phandle"
0090
0091 nvidia,xbar-cfg:
0092 description: 5 cells containing the crossbar configuration.
0093 Each lane of the SOR, identified by the cell's index, is
0094 mapped via the crossbar to the pad specified by the cell's
0095 value.
0096 $ref: "/schemas/types.yaml#/definitions/uint32-array"
0097
0098 # optional when driving an eDP output
0099 nvidia,dpaux:
0100 description: phandle to a DispayPort AUX interface
0101 $ref: "/schemas/types.yaml#/definitions/phandle"
0102
0103 allOf:
0104 - if:
0105 properties:
0106 compatible:
0107 contains:
0108 enum:
0109 - nvidia,tegra186-sor
0110 - nvidia,tegra194-sor
0111 then:
0112 properties:
0113 clocks:
0114 items:
0115 - description: clock input for the SOR hardware
0116 - description: SOR output clock
0117 - description: input for the pixel clock
0118 - description: reference clock for the SOR clock
0119 - description: safe reference clock for the SOR clock
0120 during power up
0121 - description: SOR pad output clock
0122
0123 clock-names:
0124 items:
0125 - const: sor
0126 - enum:
0127 - source # deprecated
0128 - out
0129 - const: parent
0130 - const: dp
0131 - const: safe
0132 - const: pad
0133 else:
0134 properties:
0135 clocks:
0136 items:
0137 - description: clock input for the SOR hardware
0138 - description: SOR output clock
0139 - description: input for the pixel clock
0140 - description: reference clock for the SOR clock
0141 - description: safe reference clock for the SOR clock
0142 during power up
0143
0144 clock-names:
0145 items:
0146 - const: sor
0147 - enum:
0148 - source # deprecated
0149 - out
0150 - const: parent
0151 - const: dp
0152 - const: safe
0153
0154 additionalProperties: false
0155
0156 required:
0157 - compatible
0158 - reg
0159 - interrupts
0160 - clocks
0161 - clock-names
0162 - resets
0163 - reset-names
0164 - avdd-io-hdmi-dp-supply
0165 - vdd-hdmi-dp-pll-supply
0166
0167 examples:
0168 - |
0169 #include <dt-bindings/clock/tegra210-car.h>
0170 #include <dt-bindings/gpio/tegra-gpio.h>
0171 #include <dt-bindings/interrupt-controller/arm-gic.h>
0172
0173 sor0: sor@54540000 {
0174 compatible = "nvidia,tegra210-sor";
0175 reg = <0x54540000 0x00040000>;
0176 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0177 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
0178 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
0179 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
0180 <&tegra_car TEGRA210_CLK_PLL_DP>,
0181 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
0182 clock-names = "sor", "out", "parent", "dp", "safe";
0183 resets = <&tegra_car 182>;
0184 reset-names = "sor";
0185 pinctrl-0 = <&state_dpaux_aux>;
0186 pinctrl-1 = <&state_dpaux_i2c>;
0187 pinctrl-2 = <&state_dpaux_off>;
0188 pinctrl-names = "aux", "i2c", "off";
0189 power-domains = <&pd_sor>;
0190
0191 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
0192 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
0193 hdmi-supply = <&vdd_hdmi>;
0194
0195 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0196 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
0197 };
