0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra MIPI pad calibration controller
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012
0013 properties:
0014 $nodename:
0015 pattern: "^mipi@[0-9a-f]+$"
0016
0017 compatible:
0018 enum:
0019 - nvidia,tegra114-mipi
0020 - nvidia,tegra210-mipi
0021 - nvidia,tegra186-mipi
0022
0023 reg:
0024 maxItems: 1
0025
0026 clocks:
0027 items:
0028 - description: module clock
0029
0030 clock-names:
0031 items:
0032 - const: mipi-cal
0033
0034 power-domains:
0035 maxItems: 1
0036
0037 "#nvidia,mipi-calibrate-cells":
0038 description: The number of cells in a MIPI calibration specifier.
0039 Should be 1. The single cell specifies a bitmask of the pads that
0040 need to be calibrated for a given device.
0041 $ref: "/schemas/types.yaml#/definitions/uint32"
0042 const: 1
0043
0044 additionalProperties: false
0045
0046 required:
0047 - compatible
0048 - reg
0049 - clocks
0050 - "#nvidia,mipi-calibrate-cells"
0051
0052 examples:
0053 - |
0054 #include <dt-bindings/clock/tegra114-car.h>
0055
0056 mipi@700e3000 {
0057 compatible = "nvidia,tegra114-mipi";
0058 reg = <0x700e3000 0x100>;
0059 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
0060 clock-names = "mipi-cal";
0061 #nvidia,mipi-calibrate-cells = <1>;
0062 };
0063
0064 dsia: dsi@54300000 {
0065 compatible = "nvidia,tegra114-dsi";
0066 reg = <0x54300000 0x00040000>;
0067 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
0068 <&tegra_car TEGRA114_CLK_DSIALP>,
0069 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
0070 clock-names = "dsi", "lp", "parent";
0071 resets = <&tegra_car 48>;
0072 reset-names = "dsi";
0073 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
0074 };
